Lines Matching defs:Size
274 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
1894 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1944 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2041 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2058 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2108 if (ValLocs.size() != 1)
2157 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2205 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2263 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2316 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2414 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2470 unsigned Size = VT.getSizeInBits()/8;
2471 Len -= Size;
2472 Dest.Offset += Size;
2473 Src.Offset += Size;
2570 // The high bits for a type smaller than the register size are assumed to be
