Lines Matching defs:N0
4171 /// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
4183 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
4184 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
4225 /// vrev: N0 = [k1 k0 k3 k2 ]
4243 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
4244 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
5860 SDNode *N0 = N->getOperand(0).getNode();
5862 return N0->hasOneUse() && N1->hasOneUse() &&
5863 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
5871 SDNode *N0 = N->getOperand(0).getNode();
5873 return N0->hasOneUse() && N1->hasOneUse() &&
5874 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
5885 SDNode *N0 = Op.getOperand(0).getNode();
5889 bool isN0SExt = isSignExtended(N0, DAG);
5894 bool isN0ZExt = isZeroExtended(N0, DAG);
5901 if (isN1SExt && isAddSubSExt(N0, DAG)) {
5904 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
5908 std::swap(N0, N1);
5929 Op0 = SkipExtensionForVMULL(N0, DAG);
5944 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
5945 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
5947 return DAG.getNode(N0->getOpcode(), DL, VT,
5984 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
5989 N0N0);
5991 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6007 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6008 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6011 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6012 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6015 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6016 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6017 return N0;
6026 SDValue N0 = Op.getOperand(0);
6031 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
6034 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6038 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6043 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
6046 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6047 N0 = LowerCONCAT_VECTORS(N0, DAG);
6049 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
6050 return N0;
6052 return LowerSDIV_v4i16(N0, N1, dl, DAG);
6061 SDValue N0 = Op.getOperand(0);
6066 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
6069 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6073 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6078 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
6081 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6082 N0 = LowerCONCAT_VECTORS(N0, DAG);
6084 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
6086 N0);
6087 return N0;
6093 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
6095 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6116 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6117 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6120 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6121 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6124 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6125 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6126 return N0;
7737 SDValue N0 = N->getOperand(0);
7739 if (N0.getNode()->hasOneUse()) {
7740 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
7745 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
7754 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
7761 || N0.getOpcode() != ISD::BUILD_VECTOR
7771 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
7777 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7779 SDValue Vec = N0->getOperand(0)->getOperand(0);
7786 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
7787 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
7790 SDValue ExtVec0 = N0->getOperand(i);
7997 /// operands N0 and N1. This is a helper for PerformADDCombine that is
8000 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
8005 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
8010 if (N0.getNode()->hasOneUse()) {
8011 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
8022 SDValue N0 = N->getOperand(0);
8026 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
8031 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
8038 SDValue N0 = N->getOperand(0);
8043 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
8072 SDValue N0 = N->getOperand(0);
8074 unsigned Opcode = N0.getOpcode();
8081 std::swap(N0, N1);
8084 if (N0 == N1)
8089 SDValue N00 = N0->getOperand(0);
8090 SDValue N01 = N0->getOperand(1);
8266 SDValue N0 = N->getOperand(0);
8267 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
8279 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
8295 N0->getOperand(1),
8296 N0->getOperand(0),
8325 SDValue N00 = N0.getOperand(0);
8330 SDValue MaskOp = N0.getOperand(1);
9281 SDValue N0 = Op->getOperand(0);
9305 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
9568 SDValue N0 = N->getOperand(0);
9569 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
9570 DAG.MaskedValueIsZero(N0.getOperand(0),
9572 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
9609 SDValue N0 = N->getOperand(0);
9615 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9616 SDValue Vec = N0.getOperand(0);
9617 SDValue Lane = N0.getOperand(1);
9619 EVT EltVT = N0.getValueType();
