Lines Matching full:bits
18 class Format<bits<6> val> {
19 bits<6> Value = val;
90 class AddrMode<bits<5> val> {
91 bits<5> Value = val;
112 class IndexMode<bits<2> val> {
113 bits<2> Value = val;
121 class Domain<bits<3> val> {
122 bits<3> Value = val;
286 bits<2> IndexModeBits = IM.Value;
288 bits<6> Form = F.Value;
314 field bits<32> Inst;
315 // Mask of bits that cause an encoding to be UNPREDICTABLE.
319 field bits<32> Unpredictable = 0;
322 field bits<32> SoftFail = Unpredictable;
331 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
423 bits<4> p;
454 bits<4> p; // Predicate operand
455 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
500 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
506 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
519 class AIldr_ex_or_acq<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin,
523 bits<4> Rt;
524 bits<4> addr;
534 class AIstr_ex_or_rel<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin,
538 bits<4> Rt;
539 bits<4> addr;
550 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
554 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
557 bits<4> Rd;
563 class AIldaex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
568 class AIstlex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
572 bits<4> Rd;
578 bits<4> Rt;
579 bits<4> Rt2;
580 bits<4> addr;
593 class AIldracq<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
598 class AIstrrel<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
606 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
613 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
620 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
631 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
649 bits<4> Rt;
665 bits<14> offset;
666 bits<4> Rn;
683 bits<14> offset;
684 bits<4> Rn;
704 bits<18> addr;
712 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
716 bits<14> addr;
717 bits<4> Rt;
733 class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops,
738 bits<4> Rt;
749 class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops,
758 bits<4> addr;
759 bits<4> Rt;
770 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
774 bits<14> addr;
775 bits<4> Rt;
794 bits<4> p;
795 bits<16> regs;
796 bits<4> Rn;
805 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
813 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
822 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
826 bits<4> Rd;
827 bits<4> Rn;
828 bits<4> Rm;
837 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
840 bits<4> Ra;
845 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
849 bits<4> Rn;
850 bits<4> Rm;
859 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
862 bits<4> Rd;
867 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
870 bits<4> Ra;
874 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
877 bits<4> RdLo;
878 bits<4> RdHi;
884 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
889 bits<4> Rd;
890 bits<4> Rm;
901 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
905 bits<4> Rd;
906 bits<4> Rm;
916 class ADivA1I<bits<3> opcod, dag oops, dag iops,
920 bits<4> Rd;
921 bits<4> Rn;
922 bits<4> Rm;
950 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
954 bits<4> Rd;
955 bits<4> Rn;
956 bits<4> Rm;
957 bits<5> sh;
1017 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
1111 class T1Encoding<bits<6> opcode> : Encoding16 {
1116 class T1General<bits<5> opcode> : Encoding16 {
1122 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1128 class T1Special<bits<4> opcode> : Encoding16 {
1134 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1138 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1140 class T1BranchCond<bits<4> opcode> : Encoding16 {
1145 // following bits are used for "opA" (see A6.2.4):
1150 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1155 bits<3> Rt;
1156 bits<8> addr;
1161 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1166 bits<3> Rt;
1167 bits<8> addr;
1174 class T1Misc<bits<7> opcode> : Encoding16 {
1202 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1257 bits<4> Rt;
1258 bits<4> Rt2;
1259 bits<13> addr;
1276 bits<4> Rt;
1277 bits<4> Rt2;
1278 bits<4> addr;
1279 bits<9> imm;
1304 class T2Cop<bits<4> opc, dag oops, dag iops, string opcstr, string asm,
1316 class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre,
1328 bits<4> Rt;
1329 bits<13> addr;
1349 class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre,
1361 bits<4> Rt;
1362 bits<4> Rn;
1363 bits<9> offset;
1413 bits<4> p;
1429 bits<4> p;
1448 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1454 bits<5> Dd;
1455 bits<13> addr;
1473 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1479 bits<5> Sd;
1480 bits<13> addr;
1517 bits<4> Rn;
1518 bits<13> regs;
1537 bits<4> Rn;
1538 bits<13> regs;
1558 bits<4> Rn;
1559 bits<13> regs;
1573 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1578 bits<5> Dd;
1579 bits<5> Dm;
1599 class ADuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1604 bits<5> Dd;
1605 bits<5> Dm;
1625 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1630 bits<5> Dd;
1631 bits<5> Dn;
1632 bits<5> Dm;
1653 class ADbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
1659 bits<5> Dd;
1660 bits<5> Dn;
1661 bits<5> Dm;
1684 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1689 bits<5> Sd;
1690 bits<5> Sm;
1708 class ASuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1714 bits<5> Sd;
1715 bits<5> Sm;
1736 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1745 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1749 bits<5> Sd;
1750 bits<5> Sn;
1751 bits<5> Sm;
1770 class ASbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
1776 bits<5> Sd;
1777 bits<5> Sn;
1778 bits<5> Sm;
1800 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1807 bits<5> Sd;
1808 bits<5> Sn;
1809 bits<5> Sm;
1821 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1834 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1838 bits<5> fbits;
1846 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1854 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1863 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1867 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1871 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1875 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1925 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1939 bits<5> Vd;
1940 bits<6> Rn;
1941 bits<4> Rm;
1949 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1954 bits<3> lane;
1994 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
2009 bits<5> Vd;
2010 bits<13> SIMM;
2021 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
2022 bits<5> op11_7, bit op6, bit op4,
2035 bits<5> Vd;
2036 bits<5> Vm;
2045 class N2Vnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
2050 bits<5> Vd;
2051 bits<5> Vm;
2059 // Encode constant bits
2074 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
2075 bits<5> op11_7, bit op6, bit op4,
2088 bits<5> Vd;
2089 bits<5> Vm;
2098 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2110 bits<5> Vd;
2111 bits<5> Vm;
2112 bits<6> SIMM;
2123 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2136 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
2142 bits<5> Vd;
2143 bits<5> Vn;
2144 bits<5> Vm;
2154 class N3Vnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2159 bits<5> Vd;
2160 bits<5> Vn;
2161 bits<5> Vm;
2171 // Encode constant bits
2179 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2187 bits<5> Vd;
2188 bits<5> Vn;
2189 bits<5> Vm;
2200 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2208 bits<5> Vd;
2209 bits<5> Vn;
2210 bits<5> Vm;
2211 bits<2> lane;
2223 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2236 bits<5> Vd;
2237 bits<5> Vn;
2238 bits<5> Vm;
2249 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2270 bits<5> V;
2271 bits<4> R;
2272 bits<4> p;
2273 bits<4> lane;
2280 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2285 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2290 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2297 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
2308 bits<5> Vd;
2309 bits<5> Vm;
