Lines Matching full:b00
600 let Inst{7-6} = 0b00; // imm2
601 let Inst{5-4} = 0b00; // type
684 let Inst{7-6} = 0b00; // imm2
685 let Inst{5-4} = 0b00; // type
805 let Inst{7-6} = 0b00; // imm2
806 let Inst{5-4} = 0b00; // type
847 let Inst{7-6} = 0b00; // imm2
848 let Inst{5-4} = 0b00; // type
945 let Inst{7-6} = 0b00; // imm2
946 let Inst{5-4} = 0b00; // type
997 let Inst{26-25} = 0b00;
1017 let Inst{26-25} = 0b00;
1042 let Inst{26-25} = 0b00;
1267 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1273 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1341 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1346 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1361 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1367 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1392 let Inst{26-25} = 0b00;
1407 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1409 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1433 def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt),
1441 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1467 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1494 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1535 let Inst{26-25} = 0b00;
1551 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1601 def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1712 let Inst{26-25} = 0b00;
1727 let Inst{26-25} = 0b00;
1742 let Inst{26-25} = 0b00;
1757 let Inst{26-25} = 0b00;
1781 let Inst{26-25} = 0b00;
1799 let Inst{26-25} = 0b00;
1817 let Inst{26-25} = 0b00;
1835 let Inst{26-25} = 0b00;
2262 let Inst{7-6} = 0b00; // imm2 = '00'
2263 let Inst{5-4} = 0b00;
2285 let Inst{7-6} = 0b00; // imm2 = '00'
2286 let Inst{5-4} = 0b00;
2296 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2495 let Inst{7-6} = 0b00; // imm2
2496 let Inst{5-4} = 0b00; // type
2685 let Inst{7-6} = 0b00;
2686 let Inst{5-4} = 0b00;
2698 let Inst{7-6} = 0b00;
2711 let Inst{7-6} = 0b00;
2724 let Inst{7-6} = 0b00;
2736 let Inst{7-6} = 0b00;
2737 let Inst{5-4} = 0b00;
2748 let Inst{7-6} = 0b00;
2765 let Inst{7-6} = 0b00;
2766 let Inst{5-4} = 0b00;
2778 let Inst{7-6} = 0b00;
2791 let Inst{7-6} = 0b00;
2804 let Inst{7-6} = 0b00;
2816 let Inst{7-6} = 0b00;
2817 let Inst{5-4} = 0b00;
2828 let Inst{7-6} = 0b00;
2956 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2965 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3067 def t2CRC32B : T2I_crc32<0, 0b00, "b", int_arm_crc32b>;
3068 def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>;
3114 let Inst{7-6} = 0b00; // imm2
3115 let Inst{5-4} = 0b00; // type
3774 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3776 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
4106 let Inst{9-8} = 0b00;
