Lines Matching defs:newOpc
7869 unsigned NewOpc;
7872 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7873 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7874 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7878 TmpInst.setOpcode(NewOpc);
7905 unsigned newOpc;
7908 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7909 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7910 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7911 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7913 TmpInst.setOpcode(newOpc);
7939 unsigned newOpc;
7942 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7943 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7944 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7945 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7946 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7950 TmpInst.setOpcode(newOpc);
7956 if (newOpc != ARM::t2RRX)
8343 unsigned NewOpc;
8346 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
8347 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
8348 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
8349 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
8353 TmpInst.setOpcode(NewOpc);
8388 unsigned newOpc;
8393 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
8394 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
8395 case ARM::EORrsi: newOpc = ARM::EORrr; break;
8396 case ARM::BICrsi: newOpc = ARM::BICrr; break;
8397 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
8398 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
8405 TmpInst.setOpcode(newOpc);
8458 unsigned NewOpc;
8461 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8462 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8463 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8464 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8465 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8466 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8469 TmpInst.setOpcode(NewOpc);
8498 unsigned NewOpc;
8501 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8502 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8503 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8504 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8507 TmpInst.setOpcode(NewOpc);
