Lines Matching refs:OpIdx
81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
125 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
134 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
137 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
143 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
146 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
149 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
156 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
161 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
167 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
173 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
179 uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
186 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
191 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
194 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
218 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
223 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
228 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
233 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
238 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
244 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
249 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
254 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
259 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
558 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
561 const MCOperand &MO = MI.getOperand(OpIdx);
562 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
587 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
591 const MCOperand &MO = MI.getOperand(OpIdx);
625 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
628 const MCOperand MO = MI.getOperand(OpIdx);
630 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
638 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
641 const MCOperand MO = MI.getOperand(OpIdx);
643 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
650 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
653 const MCOperand MO = MI.getOperand(OpIdx);
655 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
662 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
665 const MCOperand MO = MI.getOperand(OpIdx);
667 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
674 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
677 const MCOperand MO = MI.getOperand(OpIdx);
679 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
703 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
710 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
711 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
717 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
720 const MCOperand MO = MI.getOperand(OpIdx);
723 return ::getBranchTargetOpValue(MI, OpIdx,
725 return ::getBranchTargetOpValue(MI, OpIdx,
733 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
736 const MCOperand MO = MI.getOperand(OpIdx);
739 return ::getBranchTargetOpValue(MI, OpIdx,
741 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
748 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
751 const MCOperand MO = MI.getOperand(OpIdx);
753 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
761 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
765 const MCOperand MO = MI.getOperand(OpIdx);
768 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
791 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
794 const MCOperand MO = MI.getOperand(OpIdx);
796 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
832 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
835 const MCOperand MO = MI.getOperand(OpIdx);
837 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
852 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
855 const MCOperand MO = MI.getOperand(OpIdx);
857 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
865 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
871 const MCOperand &MO1 = MI.getOperand(OpIdx);
872 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
880 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
889 const MCOperand &MO = MI.getOperand(OpIdx);
919 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
932 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
944 int32_t Imm8 = MI.getOperand(OpIdx).getImm();
964 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
973 const MCOperand &MO = MI.getOperand(OpIdx);
986 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1005 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1010 const MCOperand &MO = MI.getOperand(OpIdx);
1011 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1018 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1023 const MCOperand &MO = MI.getOperand(OpIdx);
1074 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1077 const MCOperand &MO = MI.getOperand(OpIdx);
1078 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1079 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1108 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
1115 const MCOperand &MO = MI.getOperand(OpIdx);
1117 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups, STI);
1123 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1129 const MCOperand &MO = MI.getOperand(OpIdx);
1130 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1146 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1151 const MCOperand &MO = MI.getOperand(OpIdx);
1152 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1158 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1165 const MCOperand &MO = MI.getOperand(OpIdx);
1166 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1178 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1186 const MCOperand &MO = MI.getOperand(OpIdx);
1187 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1188 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1215 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1220 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1221 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1231 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1237 OpIdx);
1238 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1246 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1249 const MCOperand MO = MI.getOperand(OpIdx);
1251 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1257 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1266 const MCOperand &MO = MI.getOperand(OpIdx);
1283 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1296 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1309 const MCOperand &MO = MI.getOperand(OpIdx);
1310 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1311 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1344 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1355 const MCOperand &MO = MI.getOperand(OpIdx);
1356 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1466 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1477 const MCOperand &MO = MI.getOperand(OpIdx);
1478 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
