Lines Matching defs:End
213 if (F == Map.end())
223 if (F == Map.end())
234 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
238 return LI.end();
244 LiveInterval::iterator P = LI.end();
245 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
246 if (I->end > S)
280 // live segments that begin with a register, and end at a block boundary.
286 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
287 if (!I->start.isRegister() || !I->end.isBlock())
333 LiveInterval::iterator End = LI.end();
336 assert(T != End);
338 if (N != End)
339 T->end = N->start;
341 T->end = LIS->getMBBEndIdx(MI->getParent());
351 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
352 SlotIndex EX = I->end;
378 if (LT == LI.end())
382 SlotIndex EX = LT->end;
383 LT->end = S;
384 // If LT does not end at a block boundary, the termination is done.
392 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
438 if (LT != LID.end())
446 if (N == LID.end()) {
447 // There is no live segment after MX. End this segment at the end of
451 // If the next segment starts at the block boundary, end the new segment
453 // Otherwise, end the segment at the beginning of the next segment. In
467 if (P == LID.end())
470 // If the previous segment extends to the end of the previous block,
471 // the end index may actually be the beginning of this block. If
474 SlotIndex PE = P->end.isBlock() ? P->end.getPrevIndex() : P->end;
483 P->end = MX;
490 if (N != LID.end())
511 if (P == LIU.end())
514 assert(P != LIU.end() && "MI uses undefined register?");
515 SlotIndex EX = P->end;
522 P->end = MX.getNextIndex();
549 assert(LT != LID.end() && "Expecting live segments");
559 // the end of the current one, and merge the value numbers.
560 // Otherwise, remove the current segment, and make the end of it "undef".
562 SlotIndex PE = P->end.isBlock() ? P->end.getPrevIndex() : P->end;
566 makeDefined(DefR, LT->end, false);
571 P->end = LT->start;
578 while (N != LID.end()) {
586 if (N->end.isRegister()) {
587 makeDefined(DefR, N->end, false);
599 for (LiveInterval::iterator I = LID.begin(), E = LID.end(); I != E; ++I) {
648 assert(VC->begin() != VC->end() && "Empty register class");
732 for (I = B.begin(), E = B.end(); I != E; I = NextI) {
934 MachineBasicBlock::iterator End = std::next(Last);
935 for (MachineBasicBlock::iterator I = First; I != End; ++I) {
1085 for (I = B.begin(), E = B.end(); I != E; I = NextI) {
1113 for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) {
1128 for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) {
1165 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
1170 // ...and end in a register or in a dead slot.
1171 if (!LR.end.isRegister() && !LR.end.isDead())
1216 for (LiveInterval::iterator I = L2.begin(), E = L2.end(); I != E; ++I) {
1219 if (F == VM.end()) {
1225 L1.addSegment(LiveRange::Segment(I->start, I->end, NewVN));
1227 while (L2.begin() != L2.end())
1240 /// instruction in the end instead of two.
1243 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
1245 for (MachineBasicBlock::iterator J = B.begin(), F = B.end(); J != F; ++J) {
1267 // If vreg0 was coalesced with vreg1, we could end up with the following
1311 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
1324 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
