Lines Matching refs:v4i16
170 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
251 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
965 if (VT.getSimpleVT() == MVT::v4i16)
1077 if (VT == MVT::v4i16) {
1276 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1280 // Custom lower v4i16 load only. Let v4i16 store to be
1282 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1283 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::i64);
1284 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
1285 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::i64);
1355 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
1969 if (VT.getSimpleVT() == MVT::v4i16) {
2023 if ((VT.getSimpleVT() == MVT::v4i8 || VT.getSimpleVT() == MVT::v4i16) &&
2065 SDValue pack = DAG.getNode(HexagonISD::PACKHL, dl, MVT::v4i16,
2161 // We are trying to concat two v2i16 to a single v4i16.
2235 } else if ((VecVT.getSimpleVT() == MVT::v4i16) &&
2237 // v4i16 -> v2i16/i32 vselect.
