Lines Matching full:b00
88 let Inst{3-2} = 0b00;
92 def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
272 let Inst{3-2} = 0b00;
277 def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>;
449 def A2_andir : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
493 let Inst{27-26} = 0b00;
1063 def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>;
1067 def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>;
1072 def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>;
1076 def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>;
1081 def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>;
1087 def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>;
1094 def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>;
1100 def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>;
1351 def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>;
1398 let Inst{22-21} = 0b00;
1569 let Inst{9-8} = !if (isPred, Pu, 0b00);
1840 let Inst{13-12} = 0b00;
1960 let Inst{13-12} = 0b00;
2205 let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00);
2361 def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>;
2362 def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>;
2371 def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>;
2372 def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>;
2381 def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>;
2382 def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>;
2393 def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>;
2394 def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>;
2402 def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>;
2403 def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>;
2446 def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>;
2447 def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>;
2456 def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>;
2457 def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>;
2466 def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>;
2467 def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>;
2476 def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>;
2477 def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>;
2486 def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>;
2487 def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>;
2496 def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>;
2497 def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>;
2540 def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>;
2545 def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>;
2550 def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>;
2555 def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>;
2560 def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>;
2565 def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>;
2570 def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>;
2575 def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>;
2779 let Inst{27-26} = 0b00;
3071 def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>;
3076 def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>;
3081 def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>;
3086 def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>;
3092 def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>;
3097 def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>;
3738 def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>;
3823 def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>;
3897 def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>;
3964 def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>;
3965 def S2_vsxthw : T_S2op_1_di <"vsxthw", 0b00, 0b100>;
3966 def S2_vzxtbh : T_S2op_1_di <"vzxtbh", 0b00, 0b010>;
3967 def S2_vzxthw : T_S2op_1_di <"vzxthw", 0b00, 0b110>;
3985 def S2_vsathb : T_S2op_1_id <"vsathb", 0b00, 0b110>;
3986 def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>;
3987 def S2_vsatwh : T_S2op_1_id <"vsatwh", 0b00, 0b010>;
3988 def S2_vsatwuh : T_S2op_1_id <"vsatwuh", 0b00, 0b100>;
4138 def S2_vsathb_nopack : T_S2op_3 <"vsathb", 0b00, 0b111>;
4139 def S2_vsathub_nopack : T_S2op_3 <"vsathub", 0b00, 0b100>;
4140 def S2_vsatwh_nopack : T_S2op_3 <"vsatwh", 0b00, 0b110>;
4141 def S2_vsatwuh_nopack : T_S2op_3 <"vsatwuh", 0b00, 0b101>;
4169 let Inst{25-24} = 0b00;
4238 def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>;
4681 defm J2_jumprz : J2_jump_compare_0<"!=", 0b00>;
5289 defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>;
5303 def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>;
5322 defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>;
5356 def S2_shuffeb : T_S3op_64 < "shuffeb", 0b00, 0b010, 0>;
5357 def S2_shuffeh : T_S3op_64 < "shuffeh", 0b00, 0b110, 0>;
5358 def S2_shuffob : T_S3op_64 < "shuffob", 0b00, 0b100, 1>;
5425 : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>;
5441 def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>;
5448 def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>;
5458 def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>;
5487 def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>;
5529 let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10);
5669 def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>;
5675 def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>;
5740 def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>;
