Lines Matching full:bits
40 bits<32> imm;
127 class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp,
163 class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
173 bits<2> Pd;
174 bits<5> Rs;
175 bits<5> Rt;
207 class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
222 bits<2> Pd;
223 bits<5> Rs;
224 bits<8> Imm;
255 bits<5> Rd;
256 bits<5> Rs;
257 bits<8> s8;
294 class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
296 bits<5> Rdd;
297 bits<5> Rs;
298 bits<8> s8;
331 bits<5> Rdd;
332 bits<8> s8;
333 bits<6> U6;
395 class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>:
400 bits<7> name;
401 bits<5> dst1;
402 bits<5> dst2;
403 bits<6> addr;
448 bits<4> MajOp>
452 bits<5> dst;
453 bits<5> src1;
454 bits<2> src2;
455 bits<6> src3;
524 class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
528 bits<5> dst;
529 bits<5> src1;
530 bits<5> src2;
531 bits<2> u2;
549 class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
556 bits<5> dst;
557 bits<2> src1;
558 bits<5> src2;
559 bits<5> src3;
560 bits<2> u2;
585 bits<3> MajOp > {
675 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
679 bits<5> dst;
680 bits<6> addr;
681 bits<5> src;
710 class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp,
715 bits<5> dst;
716 bits<6> addr;
717 bits<3> src;
741 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
747 bits<5> src1;
748 bits<2> src2;
749 bits<6> src3;
750 bits<5> src4;
801 class T_StoreAbsRegNV <string mnemonic, string CextOp, bits<2> MajOp,
806 bits<5> src1;
807 bits<2> src2;
808 bits<6> src3;
809 bits<3> src4;
835 class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
840 bits<5> Rs;
841 bits<5> Ru;
842 bits<2> u2;
843 bits<5> Rt;
861 class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
869 bits<2> Pv;
870 bits<5> Rs;
871 bits<5> Ru;
872 bits<2> u2;
873 bits<5> Rt;
897 class T_store_new_rr <string mnemonic, bits<2> MajOp> :
902 bits<5> Rs;
903 bits<5> Ru;
904 bits<2> u2;
905 bits<3> Nt;
923 class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
929 bits<2> Pv;
930 bits<5> Rs;
931 bits<5> Ru;
932 bits<2> u2;
933 bits<3> Nt;
958 bits<3> MajOp, bit isH = 0> {
978 bits<2> MajOp> {
1040 class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
1045 bits<5> Rs;
1046 bits<8> S8;
1047 bits<8> offset;
1048 bits<6> offsetBits;
1067 class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1075 bits<2> Pv;
1076 bits<5> Rs;
1077 bits<6> S6;
1078 bits<8> offset;
1079 bits<6> offsetBits;
1109 multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
1117 bits<2> MajOp> {
1234 Operand ImmOp, bits<2>MajOp>
1239 bits<5> src1;
1240 bits<13> src2; // Actual address offset
1241 bits<3> src3;
1242 bits<11> offsetBits; // Represents offset encoding
1270 bits<2>MajOp, bit PredNot, bit isPredNew>
1276 bits<2> src1;
1277 bits<5> src2;
1278 bits<9> src3;
1279 bits<3> src4;
1280 bits<6> offsetBits; // Represents offset encoding
1316 Operand ImmOp, Operand predImmOp, bits<2> MajOp> {
1355 class T_loadalign_pr <string mnemonic, bits<4> MajOp, MemAccessSize AccessSz>
1360 bits<5> dst;
1361 bits<5> src2;
1362 bits<1> src3;
1385 class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp >
1391 bits<5> src1;
1392 bits<3> src2;
1393 bits<7> offset;
1394 bits<4> offsetBits;
1419 bits<2> MajOp, bit isPredNot, bit isPredNew >
1427 bits<2> src1;
1428 bits<5> src2;
1429 bits<3> src3;
1430 bits<7> offset;
1431 bits<4> offsetBits;
1454 bits<2> MajOp, bit PredNot> {
1462 bits<2> MajOp> {
1485 class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
1490 bits<5> src1;
1491 bits<1> src2;
1492 bits<3> src3;
1537 class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum,
1546 bits<5> src1;
1547 bits<5> src2;
1548 bits<3> Ns; // New-Value Operand
1549 bits<5> RegOp; // Non-New-Value Operand
1550 bits<11> offset;
1571 multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
1582 multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
1612 class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
1623 bits<3> src1;
1624 bits<5> src2;
1625 bits<11> offset;
1638 multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
1645 multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
1670 class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal,
1682 bits<3> src1;
1683 bits<11> offset;
1694 multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
1702 multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
1727 bits<5> Rs;
1746 bits<5> Rd;
1747 bits<6> u6;
1758 class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg>
1764 bits<2> Pd;
1765 bits<2> Ps;
1766 bits<2> Pt;
1767 bits<2> Pu;
1873 bits<5> Rd;
1874 bits<5> Rs;
1875 bits<5> Rt;
1894 bits<5> Rd;
1895 bits<5> Rs;
1896 bits<5> Ru;
1897 bits<6> s6;
1916 bits<5> Rd;
1917 bits<5> Rs;
1918 bits<6> s6;
1919 bits<5> Ru;
1997 bits<5> Rxx;
1998 bits<5> Rss;
1999 bits<5> Rtt;
2018 bits<5> Rdd;
2019 bits<5> Rss;
2020 bits<5> Rt;
2021 bits<2> u2;
2042 bits<5> Rxx;
2043 bits<5> Rss;
2044 bits<5> Rt;
2045 bits<2> u2;
2064 bits<5> Rxx;
2065 bits<5> Rss;
2066 bits<5> Rt;
2100 bits<5> Rx;
2101 bits<5> Ru;
2102 bits<10> s10;
2118 bits<5> Rd;
2119 bits<5> Rs;
2120 bits<5> Rt;
2134 bits<5> Rd;
2135 bits<5> Rs;
2136 bits<5> Rt;
2150 bits<5> Rd;
2151 bits<5> Rs;
2152 bits<5> Rt;
2166 bits<5> Rd;
2167 bits<5> Rs;
2168 bits<5> Rt;
2182 bits<5> Rd;
2183 bits<5> Rs;
2184 bits<5> Rt;
2238 class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
2245 bits<5> Rx;
2246 bits<5> Rs;
2247 bits<10> s10;
2322 bits<5> Rs;
2323 bits<5> Rd;
2324 bits<6> s6;
2337 bits<5> Rs;
2338 bits<5> Rd;
2339 bits<6> s6;
2406 bits<5> Rd;
2407 bits<6> u6;
2408 bits<5> Rs;
2409 bits<6> U6;
2432 bits<5> Rd;
2433 bits<6> u6;
2434 bits<5> Rs;
2435 bits<5> Rt;
2456 bits<5> dst;
2457 bits<5> src1;
2458 bits<8> src2;
2459 bits<5> src3;
2463 bits<6> ImmValue = !if(MajOp, src2{5-0}, src2{7-2});
2491 bits<5> Rx;
2492 bits<5> Ru;
2493 bits<5> Rs;
2556 class T_vcmpImm <string Str, bits<2> cmpOp, bits<2> minOp, Operand ImmOprnd>
2561 bits<2> Pd;
2562 bits<5> Rss;
2563 bits<32> Imm;
2564 bits<8> ImmBits;
2610 bit asl_lsr, bits<2> MajOp, InstrItinClass Itin>
2617 bits<5> Rd;
2618 bits<8> u8;
2619 bits<5> Rx;
2620 bits<5> U5;
2634 multiclass T_ShiftOperate<string mnemonic, SDNode Op, bits<2> MajOp,
2684 class T_S3op_carry <string mnemonic, bits<3> MajOp>
2689 bits<5> Rdd;
2690 bits<5> Rss;
2691 bits<5> Rtt;
2692 bits<2> Pu;
2708 class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned>
2713 bits<5> Rxx;
2714 bits<5> Rss;
2715 bits<5> Ru;
2754 bits<5> Rd;
2755 bits<6> s6;
2756 bits<5> Rt;
2849 class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
2850 string memOp, bits<2> memOpBits> :
2857 bits<5> base;
2858 bits<5> delta;
2859 bits<32> offset;
2860 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2880 class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
2881 string memOp, bits<2> memOpBits> :
2889 bits<5> base;
2890 bits<5> delta;
2891 bits<32> offset;
2892 bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2
2910 multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> {
2918 multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> {
2925 multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> {
3217 bits<2> src;
3283 bits<2>MajOp, Operand AddrOp, bit isAbs, bit isHalf>
3287 bits<19> addr;
3288 bits<5> src;
3289 bits<16> offsetBits;
3314 class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
3320 bits<2> src1;
3321 bits<6> absaddr;
3322 bits<5> src2;
3345 bits<2> MajOp, bit isHalf>
3365 Operand ImmOp, bits<2> MajOp, bit isHalf = 0> {
3386 class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs>
3390 bits<19> addr;
3391 bits<3> src;
3392 bits<16> offsetBits;
3417 class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
3422 bits<2> src1;
3423 bits<6> absaddr;
3424 bits<3> src2;
3447 class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
3467 bits<2> MajOp> {
3512 Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
3522 bits<2> MajOp, bit isHalf = 0> {
3590 bits<3> MajOp, Operand AddrOp, bit isAbs>
3594 bits<5> dst;
3595 bits<19> addr;
3596 bits<16> offsetBits;
3616 bits<3> MajOp>
3636 class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
3641 bits<5> dst;
3642 bits<2> src1;
3643 bits<6> absaddr;
3666 multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bits<3> MajOp,
3675 Operand ImmOp, bits<3> MajOp> {
3711 bits<3> MajOp>
3908 bits<2> Pd;
3909 bits<5> Rss;
3910 bits<5> Rtt;
3928 bits<2> Pd;
3929 bits<5> Rss;
3930 bits<5> Rtt;
3953 bits<2> Pd;
3954 bits<5> Rs;
3955 bits<5> Rt;
3980 bits<5> Rs;
3981 bits<14> u11_3;
4003 bits<4> Rs;
4004 bits<11> r9_2;
4049 bits<4> Rs;
4050 bits<4> Rt;
4051 bits<11> r9_2;
4103 bits<4> Rs;
4104 bits<5> U5;
4105 bits<11> r9_2;
4158 bits<4> Rs;
4159 bits<11> r9_2;
4210 bits<4> Rd;
4211 bits<6> U6;
4212 bits<11> r9_2;
4230 bits<4> Rd;
4231 bits<4> Rs;
4232 bits<11> r9_2;
