Lines Matching full:src4
743 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, RC:$src4),
744 mnemonic#"($src1<<#$src2 + #$src3) = $src4"#!if(isHalf, ".h",""),
750 bits<5> src4;
761 let Inst{12-8} = src4;
779 def : Pat<(stOp (VT RC:$src4),
782 (MI IntRegs:$src1, u2ImmPred:$src2, u32ImmPred:$src3, RC:$src4)>;
784 def : Pat<(stOp (VT RC:$src4),
787 (MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
789 def : Pat<(stOp (VT RC:$src4),
791 (MI IntRegs:$src1, 0, tglobaladdr:$src3, RC:$src4)>;
804 (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
805 mnemonic#"($src1<<#$src2 + #$src3) = $src4.new">, NewValueRel {
809 bits<3> src4;
821 let Inst{10-8} = src4;
1272 (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4),
1274 ") ")#mnemonic#"($src2+#$src3) = $src4.new",
1279 bits<3> src4;
1305 let Inst{10-8} = src4;
