Lines Matching full:src2
125 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc),
128 (MSP430selectcc GR8:$src, GR8:$src2, imm:$cc))]>;
129 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc),
132 (MSP430selectcc GR16:$src, GR16:$src2, imm:$cc))]>;
345 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
346 "add.b\t{$src2, $dst}",
347 [(set GR8:$dst, (add GR8:$src, GR8:$src2)),
350 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
351 "add.w\t{$src2, $dst}",
352 [(set GR16:$dst, (add GR16:$src, GR16:$src2)),
357 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
358 "add.b\t{$src2, $dst}",
359 [(set GR8:$dst, (add GR8:$src, (load addr:$src2))),
362 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
363 "add.w\t{$src2, $dst}",
364 [(set GR16:$dst, (add GR16:$src, (load addr:$src2))),
381 (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
382 "add.b\t{$src2, $dst}",
383 [(set GR8:$dst, (add GR8:$src, imm:$src2)),
386 (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
387 "add.w\t{$src2, $dst}",
388 [(set GR16:$dst, (add GR16:$src, imm:$src2)),
432 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
433 "addc.b\t{$src2, $dst}",
434 [(set GR8:$dst, (adde GR8:$src, GR8:$src2)),
437 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
438 "addc.w\t{$src2, $dst}",
439 [(set GR16:$dst, (adde GR16:$src, GR16:$src2)),
444 (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
445 "addc.b\t{$src2, $dst}",
446 [(set GR8:$dst, (adde GR8:$src, imm:$src2)),
449 (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
450 "addc.w\t{$src2, $dst}",
451 [(set GR16:$dst, (adde GR16:$src, imm:$src2)),
455 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
456 "addc.b\t{$src2, $dst}",
457 [(set GR8:$dst, (adde GR8:$src, (load addr:$src2))),
460 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
461 "addc.w\t{$src2, $dst}",
462 [(set GR16:$dst, (adde GR16:$src, (load addr:$src2))),
506 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
507 "and.b\t{$src2, $dst}",
508 [(set GR8:$dst, (and GR8:$src, GR8:$src2)),
511 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
512 "and.w\t{$src2, $dst}",
513 [(set GR16:$dst, (and GR16:$src, GR16:$src2)),
518 (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
519 "and.b\t{$src2, $dst}",
520 [(set GR8:$dst, (and GR8:$src, imm:$src2)),
523 (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
524 "and.w\t{$src2, $dst}",
525 [(set GR16:$dst, (and GR16:$src, imm:$src2)),
529 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
530 "and.b\t{$src2, $dst}",
531 [(set GR8:$dst, (and GR8:$src, (load addr:$src2))),
534 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
535 "and.w\t{$src2, $dst}",
536 [(set GR16:$dst, (and GR16:$src, (load addr:$src2))),
590 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
591 "bis.b\t{$src2, $dst}",
592 [(set GR8:$dst, (or GR8:$src, GR8:$src2))]>;
594 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
595 "bis.w\t{$src2, $dst}",
596 [(set GR16:$dst, (or GR16:$src, GR16:$src2))]>;
600 (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
601 "bis.b\t{$src2, $dst}",
602 [(set GR8:$dst, (or GR8:$src, imm:$src2))]>;
604 (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
605 "bis.w\t{$src2, $dst}",
606 [(set GR16:$dst, (or GR16:$src, imm:$src2))]>;
609 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
610 "bis.b\t{$src2, $dst}",
611 [(set GR8:$dst, (or GR8:$src, (load addr:$src2)))]>;
613 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
614 "bis.w\t{$src2, $dst}",
615 [(set GR16:$dst, (or GR16:$src, (load addr:$src2)))]>;
662 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
663 "bic.b\t{$src2, $dst}",
664 [(set GR8:$dst, (and GR8:$src, (not GR8:$src2)))]>;
666 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
667 "bic.w\t{$src2, $dst}",
668 [(set GR16:$dst, (and GR16:$src, (not GR16:$src2)))]>;
671 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
672 "bic.b\t{$src2, $dst}",
673 [(set GR8:$dst, (and GR8:$src, (not (i8 (load addr:$src2)))))]>;
675 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
676 "bic.w\t{$src2, $dst}",
677 [(set GR16:$dst, (and GR16:$src, (not (i16 (load addr:$src2)))))]>;
703 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
704 "xor.b\t{$src2, $dst}",
705 [(set GR8:$dst, (xor GR8:$src, GR8:$src2)),
708 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
709 "xor.w\t{$src2, $dst}",
710 [(set GR16:$dst, (xor GR16:$src, GR16:$src2)),
715 (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
716 "xor.b\t{$src2, $dst}",
717 [(set GR8:$dst, (xor GR8:$src, imm:$src2)),
720 (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
721 "xor.w\t{$src2, $dst}",
722 [(set GR16:$dst, (xor GR16:$src, imm:$src2)),
726 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
727 "xor.b\t{$src2, $dst}",
728 [(set GR8:$dst, (xor GR8:$src, (load addr:$src2))),
731 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
732 "xor.w\t{$src2, $dst}",
733 [(set GR16:$dst, (xor GR16:$src, (load addr:$src2))),
785 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
786 "sub.b\t{$src2, $dst}",
787 [(set GR8:$dst, (sub GR8:$src, GR8:$src2)),
790 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
791 "sub.w\t{$src2, $dst}",
792 [(set GR16:$dst, (sub GR16:$src, GR16:$src2)),
796 (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
797 "sub.b\t{$src2, $dst}",
798 [(set GR8:$dst, (sub GR8:$src, imm:$src2)),
801 (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
802 "sub.w\t{$src2, $dst}",
803 [(set GR16:$dst, (sub GR16:$src, imm:$src2)),
807 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
808 "sub.b\t{$src2, $dst}",
809 [(set GR8:$dst, (sub GR8:$src, (load addr:$src2))),
812 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
813 "sub.w\t{$src2, $dst}",
814 [(set GR16:$dst, (sub GR16:$src, (load addr:$src2))),
868 (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
869 "subc.b\t{$src2, $dst}",
870 [(set GR8:$dst, (sube GR8:$src, GR8:$src2)),
873 (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
874 "subc.w\t{$src2, $dst}",
875 [(set GR16:$dst, (sube GR16:$src, GR16:$src2)),
879 (outs GR8:$dst), (ins GR8:$src, i8imm:$src2),
880 "subc.b\t{$src2, $dst}",
881 [(set GR8:$dst, (sube GR8:$src, imm:$src2)),
884 (outs GR16:$dst), (ins GR16:$src, i16imm:$src2),
885 "subc.w\t{$src2, $dst}",
886 [(set GR16:$dst, (sube GR16:$src, imm:$src2)),
890 (outs GR8:$dst), (ins GR8:$src, memsrc:$src2),
891 "subc.b\t{$src2, $dst}",
892 [(set GR8:$dst, (sube GR8:$src, (load addr:$src2))),
895 (outs GR16:$dst), (ins GR16:$src, memsrc:$src2),
896 "subc.w\t{$src2, $dst}",
897 [(set GR16:$dst, (sube GR16:$src, (load addr:$src2))),
998 (outs), (ins GR8:$src, GR8:$src2),
999 "cmp.b\t{$src2, $src}",
1000 [(MSP430cmp GR8:$src, GR8:$src2), (implicit SR)]>;
1002 (outs), (ins GR16:$src, GR16:$src2),
1003 "cmp.w\t{$src2, $src}",
1004 [(MSP430cmp GR16:$src, GR16:$src2), (implicit SR)]>;
1007 (outs), (ins GR8:$src, i8imm:$src2),
1008 "cmp.b\t{$src2, $src}",
1009 [(MSP430cmp GR8:$src, imm:$src2), (implicit SR)]>;
1011 (outs), (ins GR16:$src, i16imm:$src2),
1012 "cmp.w\t{$src2, $src}",
1013 [(MSP430cmp GR16:$src, imm:$src2), (implicit SR)]>;
1016 (outs), (ins memsrc:$src, i8imm:$src2),
1017 "cmp.b\t{$src2, $src}",
1019 (i8 imm:$src2)), (implicit SR)]>;
1021 (outs), (ins memsrc:$src, i16imm:$src2),
1022 "cmp.w\t{$src2, $src}",
1024 (i16 imm:$src2)), (implicit SR)]>;
1027 (outs), (ins GR8:$src, memsrc:$src2),
1028 "cmp.b\t{$src2, $src}",
1029 [(MSP430cmp GR8:$src, (load addr:$src2)),
1032 (outs), (ins GR16:$src, memsrc:$src2),
1033 "cmp.w\t{$src2, $src}",
1034 [(MSP430cmp GR16:$src, (load addr:$src2)),
1038 (outs), (ins memsrc:$src, GR8:$src2),
1039 "cmp.b\t{$src2, $src}",
1040 [(MSP430cmp (load addr:$src), GR8:$src2),
1043 (outs), (ins memsrc:$src, GR16:$src2),
1044 "cmp.w\t{$src2, $src}",
1045 [(MSP430cmp (load addr:$src), GR16:$src2),
1053 (outs), (ins GR8:$src, GR8:$src2),
1054 "bit.b\t{$src2, $src}",
1055 [(MSP430cmp (and_su GR8:$src, GR8:$src2), 0),
1058 (outs), (ins GR16:$src, GR16:$src2),
1059 "bit.w\t{$src2, $src}",
1060 [(MSP430cmp (and_su GR16:$src, GR16:$src2), 0),
1064 (outs), (ins GR8:$src, i8imm:$src2),
1065 "bit.b\t{$src2, $src}",
1066 [(MSP430cmp (and_su GR8:$src, imm:$src2), 0),
1069 (outs), (ins GR16:$src, i16imm:$src2),
1070 "bit.w\t{$src2, $src}",
1071 [(MSP430cmp (and_su GR16:$src, imm:$src2), 0),
1075 (outs), (ins GR8:$src, memdst:$src2),
1076 "bit.b\t{$src2, $src}",
1077 [(MSP430cmp (and_su GR8:$src, (load addr:$src2)), 0),
1080 (outs), (ins GR16:$src, memdst:$src2),
1081 "bit.w\t{$src2, $src}",
1082 [(MSP430cmp (and_su GR16:$src, (load addr:$src2)), 0),
1086 (outs), (ins memsrc:$src, GR8:$src2),
1087 "bit.b\t{$src2, $src}",
1088 [(MSP430cmp (and_su (load addr:$src), GR8:$src2), 0),
1091 (outs), (ins memsrc:$src, GR16:$src2),
1092 "bit.w\t{$src2, $src}",
1093 [(MSP430cmp (and_su (load addr:$src), GR16:$src2), 0),
1097 (outs), (ins memsrc:$src, i8imm:$src2),
1098 "bit.b\t{$src2, $src}",
1099 [(MSP430cmp (and_su (load addr:$src), (i8 imm:$src2)), 0),
1102 (outs), (ins memsrc:$src, i16imm:$src2),
1103 "bit.w\t{$src2, $src}",
1104 [(MSP430cmp (and_su (load addr:$src), (i16 imm:$src2)), 0),
1108 (outs), (ins memsrc:$src, memsrc:$src2),
1109 "bit.b\t{$src2, $src}",
1111 (load addr:$src2)),
1115 (outs), (ins memsrc:$src, memsrc:$src2),
1116 "bit.w\t{$src2, $src}",
1118 (load addr:$src2)),
1142 def : Pat<(add GR16:$src, (MSP430Wrapper tglobaladdr :$src2)),
1143 (ADD16ri GR16:$src, tglobaladdr:$src2)>;
1144 def : Pat<(add GR16:$src, (MSP430Wrapper texternalsym:$src2)),
1145 (ADD16ri GR16:$src, texternalsym:$src2)>;
1146 def : Pat<(add GR16:$src, (MSP430Wrapper tblockaddress:$src2)),
1147 (ADD16ri GR16:$src, tblockaddress:$src2)>;
1163 def : Pat<(addc GR16:$src, GR16:$src2),
1164 (ADD16rr GR16:$src, GR16:$src2)>;
1165 def : Pat<(addc GR16:$src, (load addr:$src2)),
1166 (ADD16rm GR16:$src, addr:$src2)>;
1167 def : Pat<(addc GR16:$src, imm:$src2),
1168 (ADD16ri GR16:$src, imm:$src2)>;
1174 def : Pat<(addc GR8:$src, GR8:$src2),
1175 (ADD8rr GR8:$src, GR8:$src2)>;
1176 def : Pat<(addc GR8:$src, (load addr:$src2)),
1177 (ADD8rm GR8:$src, addr:$src2)>;
1178 def : Pat<(addc GR8:$src, imm:$src2),
1179 (ADD8ri GR8:$src, imm:$src2)>;
1185 def : Pat<(subc GR16:$src, GR16:$src2),
1186 (SUB16rr GR16:$src, GR16:$src2)>;
1187 def : Pat<(subc GR16:$src, (load addr:$src2)),
1188 (SUB16rm GR16:$src, addr:$src2)>;
1189 def : Pat<(subc GR16:$src, imm:$src2),
1190 (SUB16ri GR16:$src, imm:$src2)>;
1196 def : Pat<(subc GR8:$src, GR8:$src2),
1197 (SUB8rr GR8:$src, GR8:$src2)>;
1198 def : Pat<(subc GR8:$src, (load addr:$src2)),
1199 (SUB8rm GR8:$src, addr:$src2)>;
1200 def : Pat<(subc GR8:$src, imm:$src2),
1201 (SUB8ri GR8:$src, imm:$src2)>;
1209 def : Pat<(MSP430cmp (trunc (and_su GR16:$src, GR16:$src2)), 0),
1211 (EXTRACT_SUBREG GR16:$src2, subreg_8bit))>;
