Cross Reference: /external/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Lines Matching refs:RegOp
1712   const MCOperand &RegOp = Inst.getOperand(0);
1713   assert(RegOp.isReg() && "expected register operand kind");
1723     tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1731     tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1740     tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1743     createShiftOr<0, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1764     tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1768     createShiftOr<16, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1769     createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1791     tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1795     createShiftOr<32, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1796     createShiftOr<16, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1797     createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1862   const MCOperand &RegOp = Inst.getOperand(0);
1863   assert(RegOp.isReg() && "expected register operand kind");
1869     tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1878     tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1883     tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1884     tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1907   const MCOperand &RegOp = Inst.getOperand(0);
1908   unsigned RegNo = RegOp.getReg();
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