Lines Matching defs:Load
49 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
55 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
85 // PowerPC has pre-inc load and store's.
116 // PowerPC does not support direct load / store of condition registers
117 setOperationAction(ISD::LOAD, MVT::i1, Custom);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
429 setOperationAction(ISD::LOAD , VT, Promote);
430 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
493 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
601 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
602 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
636 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
689 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
735 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
821 setTargetDAGCombine(ISD::LOAD);
1507 // If we happen to be doing an i64 load or store into a stack slot that has
1509 // use an indexed load or store instruction (because the offset may not be a
1513 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1555 // FIXME dl should come from parent load or store, not from address
1574 // Match LOAD (ADD (X, Lo(G))).
1676 /// can be legally represented as pre-indexed load / store address.
1699 // PowerPC doesn't have preinc load/store instructions for vectors (except
1747 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
2037 // extra load to get the address of the global.
2196 // determine if we should load from reg_save_area or overflow_area
2715 // Create load nodes to retrieve arguments from the stack.
2903 // Add DAG nodes to load the arguments or copy them out of registers. On
3184 // We need to load the argument to a virtual register if we determined
3340 // Add DAG nodes to load the arguments or copy them out of registers. On
3542 // We need to load the argument to a virtual register if we determined above
3769 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3780 // Load the LR and FP stack slot for later adjusting.
3787 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3981 // 2. Load the address of the function entry point from the function
3983 // 3. Load the TOC of the callee from the function descriptor into r2.
3984 // 4. Load the environment pointer from the function descriptor into
3998 // Load the address of the function entry point from the function
4010 // Load environment pointer into r11.
4194 // branches to the callee. The NOP will be replaced with a load instruction
4206 // We are using a target-specific load with r2 hard coded, because the
4207 // result of a target-independent load would never go directly into r2,
4381 // Load the return address and frame pointer so it can be moved somewhere else
4671 // Load the return address and frame pointer so it can be move somewhere else
4754 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4757 MemOpChains.push_back(Load.getValue(1));
4758 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4787 // load.
4800 // local variable slot, then load the whole slot into the
4815 // Load the slot into the register.
4816 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4819 MemOpChains.push_back(Load.getValue(1));
4820 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4833 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4836 MemOpChains.push_back(Load.getValue(1));
4837 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4884 // First load the argument into the next available FPR.
4888 // Next, load the argument into GPR or stack slot if needed.
4985 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4988 MemOpChains.push_back(Load.getValue(1));
4995 RegsToPass.push_back(std::make_pair(VReg, Load));
5003 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5005 MemOpChains.push_back(Load.getValue(1));
5006 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5049 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl,
5052 MemOpChains.push_back(Load.getValue(1));
5053 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5061 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5063 MemOpChains.push_back(Load.getValue(1));
5064 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5102 // Load r2 into a virtual register and store it to the TOC save area.
5230 // Load the return address and frame pointer so it can be move somewhere else
5303 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5306 MemOpChains.push_back(Load.getValue(1));
5307 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5335 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5338 MemOpChains.push_back(Load.getValue(1));
5339 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5378 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5381 MemOpChains.push_back(Load.getValue(1));
5382 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5387 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5390 MemOpChains.push_back(Load.getValue(1));
5391 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5435 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5438 MemOpChains.push_back(Load.getValue(1));
5439 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5447 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5449 MemOpChains.push_back(Load.getValue(1));
5450 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5605 // Load the old link SP.
5709 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5904 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5919 /// need for load/store combinations.
5965 // We're trying to insert a regular store, S, and then a load, L. If the
5966 // incoming value, O, is a load, we might just be able to have our load use the
5968 // that address before we can load from it. To prevent this situation, we need
5969 // to insert our load, L, into the chain as a peer of O. To do this, we give L
6036 /// need for load/store combinations.
6101 // If we have direct moves, we can do all the conversion, skip the store/load
6297 // Load the value as a double.
6349 // Load FP Control Word from low 32 bits of stack slot.
6540 // this case more efficiently than a constant pool load, lower it to the
6549 // We first build an i32 vector, load it into a QPX register,
6637 // Now load from v4i32 into the QPX register; this will extend it to
6929 // FIXME: If SplatIdx == 0 and the input came from a load, then there is
7037 // for 3-operation perms and use a constant pool load instead.
7282 // Load it out.
7306 // understand how to form the extending load.
7366 // If this load is properly aligned, then it is legal.
7376 SDValue Load;
7378 Load =
7386 Load =
7395 "Unknown addressing mode on vector load");
7396 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
7400 Vals.push_back(Load);
7401 LoadChains.push_back(Load.getValue(1));
7420 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
7423 // To lower v4i1 from a byte array, we load the byte elements of the
7520 // understand how to form the extending load.
7683 case ISD::LOAD: return LowerLOAD(Op, DAG);
7973 // The 4-byte load must be aligned, while a char or short may be
8443 // mfspr Rx,TBU # load from TBU
8444 // mfspr Ry,TB # load from TB
8445 // mfspr Rz,TBU # load from TBU
8691 // The 4-byte load must be aligned, while a char or short may be
9057 // Return true is there is a nearyby consecutive load to the one provided
9060 // indicates that it is safe to create a new consecutive load adjacent to the
9061 // load provided.
9071 // If we find a consecutive load, then we're done, otherwise, record all
9096 // load.
9722 // then we don't need the store/load pair at all.
9763 llvm_unreachable("Unexpected opcode for little endian VSX load");
9764 case ISD::LOAD: {
9769 // If the MMO suggests this isn't a load of a full vector, leave
9787 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
9790 DCI.AddToWorklist(Load.getNode());
9791 Chain = Load.getValue(1);
9793 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
9947 case ISD::LOAD: {
9967 // P8 and later hardware should just use LOAD.
9973 // This is a type-legal unaligned Altivec or QPX load.
9988 // loaded values. The trick is that the last "extra" load is not taken
9990 // last requested load), but rather sizeof(vector) - 1 bytes after the
10025 // Create the new MMO for the new base load. It is like the original MMO,
10029 // original unaligned load.
10035 // Create the new base load.
10044 // load's pointer info offset value, and thus used to calculate the
10047 // require the next load to appear to be aligned, even though it
10052 // Walk (both up and down) the chain looking for another load at the real
10053 // (aligned) offset (the alignment of the other load does not matter in
10188 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
10194 SDValue Load = N->getOperand(0);
10195 LoadSDNode *LD = cast<LoadSDNode>(Load);
10196 // Create the byte-swapping load.
10208 // If this is an i16 load, insert the truncate.
10214 // load dead.
10217 // Next, combine the load away, we give it a bogus result value but a real
10219 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
10735 // by AM is legal for this target, for a load/store of the specified type.
10801 // Just load the return address off the stack.
11058 /// getOptimalMemOpType - Returns the target specific optimal type for load
11099 /// \brief Returns true if it is beneficial to convert a load of a constant
