Lines Matching defs:Multiple
1314 // multiple elements of the buildvector are folded together into a single
1318 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1320 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1329 if (!UniquedVals[i&(Multiple-1)].getNode())
1330 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1331 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1335 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1343 for (unsigned i = 0; i != Multiple-1; ++i) {
1351 if (!UniquedVals[Multiple-1].getNode())
1353 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1358 if (!UniquedVals[Multiple-1].getNode())
1360 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1510 // multiple of 4). The extra register needed to hold the offset comes from the
1733 // LDU/STU can only handle immediates that are a multiple of 4.
2488 "ByVal alignment is not a multiple of the pointer size");
2496 // If the array member was split into multiple registers, the first
2952 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3305 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3381 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
7030 // used (perhaps because there are multiple permutes with the same shuffle
8905 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
10129 // multiple of that one. The results will be the same, so use the
10255 // chain, this transformation is more complex. Note that multiple things
