Lines Matching full:instruction
35 /// FCFID - The FCFID instruction, taking an f64 operand and producing
60 /// VPERM - The PPC VPERM Instruction.
64 /// The CMPB instruction (takes two operands of i32 or i64).
78 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
103 /// MTCTR instruction.
107 /// BCTRL instruction.
111 /// instruction and the TOC reload required on SVR4 PPC64.
117 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
160 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
198 /// TLS model, produces an ADDIS8 instruction that adds the GOT
203 /// TLS model, produces a LD instruction with base register G8RReg
209 /// model, produces an ADD instruction that adds the contents of
212 /// identifies to the linker that the instruction is part of a
217 /// model, produces an ADDIS8 instruction that adds the GOT base
222 /// model, produces an ADDI8 instruction that adds G8RReg to
238 /// model, produces an ADDIS8 instruction that adds the GOT base
243 /// model, produces an ADDI8 instruction that adds G8RReg to
259 /// model, produces an ADDIS8 instruction that adds X3 to
264 /// model, produces an ADDI8 instruction that adds G8RReg to
269 /// during instruction selection to optimize a BUILD_VECTOR into
279 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
280 /// or stxvd2x instruction. The chain is necessary because the
285 /// QVFPERM = This corresponds to the QPX qvfperm instruction.
288 /// QVGPCI = This corresponds to the QPX qvgpci instruction.
291 /// QVALIGNI = This corresponds to the QPX qvaligni instruction.
294 /// QVESPLATI = This corresponds to the QPX qvesplati instruction.
302 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
308 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
313 /// STFIWX - The STFIWX instruction. The first operand is an input token
328 /// Maps directly to an lxvd2x instruction that will be followed by
333 /// Maps directly to an stxvd2x instruction that will be preceded by
351 /// VPKUHUM instruction.
356 /// VPKUWUM instruction.
361 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
366 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
385 /// formed by using a vspltis[bhw] instruction of the specified element
480 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
482 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
616 /// or null if the target does not support "fast" instruction selection.
