Lines Matching refs:v8f32
58 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);66 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);178 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32}) {
