Cross Reference: /external/llvm/lib/Target/R600/SIInstrInfo.cpp

Lines Matching refs:TargetRegisterClass
449 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
465                                       const TargetRegisterClass *RC,
518                                        const TargetRegisterClass *RC,
885 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1319       const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1436 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1471   const TargetRegisterClass *RC = RI.getRegClass(RCID);
1479   const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1495                                          const TargetRegisterClass *SuperRC,
1497                                          const TargetRegisterClass *SubRC)
1524   const TargetRegisterClass *SuperRC,
1526   const TargetRegisterClass *SubRC) const {
1545                                     const TargetRegisterClass *RC,
1585   const TargetRegisterClass *DefinedRC =
1607     const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
1708     const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1713       const TargetRegisterClass *OpRC =
1763     const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1764     const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1907                             const TargetRegisterClass *HalfRC,
2072       const TargetRegisterClass *NewDstRC =
2272     const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
2320 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2338   const TargetRegisterClass *Src0RC = Src0.isReg() ?
2342   const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2347   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2348   const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2391   const TargetRegisterClass *Src0RC = Src0.isReg() ?
2395   const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2396   const TargetRegisterClass *Src1RC = Src1.isReg() ?
2400   const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2407   const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2408   const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2452   const TargetRegisterClass *SrcRC = Src.isReg() ?
2459   const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
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