Lines Matching full:bits
62 bits<5> AccessBytes = 0;
67 bits<4> CCValues = 0;
71 bits<4> CompareZeroCCMask = 0;
144 // bits<4> Rn : register input or output for operand n
145 // bits<m> In : immediate value of width m for operand n
146 // bits<4> BDn : address operand n, which has a base and a displacement
147 // bits<m> XBDn : address operand n, which has an index, a base and a
149 // bits<4> Xn : index register for address operand n
150 // bits<4> Mn : mode value for operand n
158 class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
160 field bits<32> Inst;
161 field bits<32> SoftFail = 0;
163 bits<4> R1;
164 bits<16> I2;
172 class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
174 field bits<48> Inst;
175 field bits<48> SoftFail = 0;
177 bits<4> R1;
178 bits<4> R2;
179 bits<4> M3;
180 bits<16> RI4;
191 class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
193 field bits<48> Inst;
194 field bits<48> SoftFail = 0;
196 bits<4> R1;
197 bits<8> I2;
198 bits<4> M3;
199 bits<16> RI4;
209 class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
211 field bits<48> Inst;
212 field bits<48> SoftFail = 0;
214 bits<4> R1;
215 bits<4> R3;
216 bits<16> I2;
226 class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
228 field bits<48> Inst;
229 field bits<48> SoftFail = 0;
231 bits<4> R1;
232 bits<4> R2;
233 bits<8> I3;
234 bits<8> I4;
235 bits<8> I5;
246 class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
248 field bits<48> Inst;
249 field bits<48> SoftFail = 0;
251 bits<4> R1;
252 bits<32> I2;
260 class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
262 field bits<16> Inst;
263 field bits<16> SoftFail = 0;
265 bits<4> R1;
266 bits<4> R2;
273 class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
275 field bits<32> Inst;
276 field bits<32> SoftFail = 0;
278 bits<4> R1;
279 bits<4> R3;
280 bits<4> R2;
289 class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
291 field bits<32> Inst;
292 field bits<32> SoftFail = 0;
294 bits<4> R1;
295 bits<4> R2;
303 class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
305 field bits<32> Inst;
306 field bits<32> SoftFail = 0;
308 bits<4> R1;
309 bits<4> R2;
310 bits<4> R3;
311 bits<4> R4;
320 class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
322 field bits<32> Inst;
323 field bits<32> SoftFail = 0;
325 bits<4> R1;
326 bits<20> XBD2;
335 class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
337 field bits<48> Inst;
338 field bits<48> SoftFail = 0;
340 bits<4> R1;
341 bits<20> XBD2;
352 class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
354 field bits<48> Inst;
355 field bits<48> SoftFail = 0;
357 bits<4> R1;
358 bits<4> R3;
359 bits<20> XBD2;
371 class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
373 field bits<48> Inst;
374 field bits<48> SoftFail = 0;
376 bits<4> R1;
377 bits<28> XBD2;
388 class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
390 field bits<32> Inst;
391 field bits<32> SoftFail = 0;
393 bits<4> R1;
394 bits<4> R3;
395 bits<16> BD2;
403 class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
405 field bits<48> Inst;
406 field bits<48> SoftFail = 0;
408 bits<4> R1;
409 bits<4> R3;
410 bits<24> BD2;
421 class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
423 field bits<32> Inst;
424 field bits<32> SoftFail = 0;
426 bits<16> BD1;
427 bits<8> I2;
434 class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
436 field bits<48> Inst;
437 field bits<48> SoftFail = 0;
439 bits<16> BD1;
440 bits<16> I2;
447 class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
449 field bits<48> Inst;
450 field bits<48> SoftFail = 0;
452 bits<24> BD1;
453 bits<8> I2;
463 class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
465 field bits<48> Inst;
466 field bits<48> SoftFail = 0;
468 bits<24> BDL1;
469 bits<16> BD2;
476 class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
478 field bits<32> Inst;
479 field bits<32> SoftFail = 0;
481 bits<16> BD2;
562 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
570 class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
579 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
585 class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
597 class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
598 RegisterOperand cls, bits<5> bytes,
609 class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
610 RegisterOperand cls, bits<5> bytes,
621 multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
623 bits<5> bytes> {
633 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
645 class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
653 class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
661 class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
669 multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
679 class CondStoreRSY<string mnemonic, bits<16> opcode,
680 RegisterOperand cls, bits<5> bytes,
692 class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
693 RegisterOperand cls, bits<5> bytes,
703 class FixedCondStoreRSY<string mnemonic, bits<16> opcode,
704 RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
714 class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
723 class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
732 class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
741 class UnaryRRF4<string mnemonic, bits<16> opcode, RegisterOperand cls1,
748 class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
759 class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
770 class FixedCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
771 RegisterOperand cls2, bits<4> ccmask>
781 class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
787 class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
793 class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
805 class CondUnaryRSY<string mnemonic, bits<16> opcode,
807 bits<5> bytes, AddressingMode mode = bdaddr20only>
824 class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
825 RegisterOperand cls, bits<5> bytes,
837 class FixedCondUnaryRSY<string mnemonic, bits<16> opcode,
838 RegisterOperand cls, bits<4> ccmask, bits<5> bytes,
850 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
851 RegisterOperand cls, bits<5> bytes,
862 class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
863 RegisterOperand cls, bits<5> bytes>
873 class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
874 RegisterOperand cls, bits<5> bytes,
885 multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
887 bits<5> bytes> {
897 class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
908 class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
919 class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
929 class BinaryRRFK<string mnemonic, bits<16> opcode, SDPatternOperator operator,
937 multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
949 multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
961 class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
970 class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
976 multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
988 class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
997 class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1007 class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1013 multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
1024 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1025 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1038 class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1039 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
1052 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1053 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1066 multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1068 SDPatternOperator load, bits<5> bytes> {
1079 class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1088 class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1097 multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
1098 bits<16> siyOpcode, SDPatternOperator operator,
1108 class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1118 class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1128 class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1136 class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1144 class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
1157 class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1158 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1170 class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1171 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
1182 class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1183 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
1195 multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
1197 SDPatternOperator load, bits<5> bytes> {
1208 class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1218 class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1227 class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1237 multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
1249 class TernaryRRD<string mnemonic, bits<16> opcode,
1260 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1261 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
1275 class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1284 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
1295 class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
1306 multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
1316 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
1326 class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
1331 class PrefetchRILPC<string mnemonic, bits<12> opcode,
1344 multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
1375 RegisterOperand cls, bits<5> bytes,
1430 SDPatternOperator load, bits<5> bytes,
1442 bits<5> bytes, AddressingMode mode = bdxaddr20only>
1544 multiclass MemorySS<string mnemonic, bits<8> opcode,
1566 multiclass StringRRE<string mnemonic, bits<16> opcode,
