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Lines Matching defs:OpReg

1443         unsigned OpReg = getRegForValue(TI->getOperand(0));
1444 if (OpReg == 0) return false;
1446 .addReg(OpReg).addImm(1);
1488 unsigned OpReg = getRegForValue(BI->getCondition());
1489 if (OpReg == 0) return false;
1492 .addReg(OpReg).addImm(1);
1505 unsigned CReg = 0, OpReg = 0;
1511 case Instruction::LShr: OpReg = X86::SHR8rCL; break;
1512 case Instruction::AShr: OpReg = X86::SAR8rCL; break;
1513 case Instruction::Shl: OpReg = X86::SHL8rCL; break;
1520 case Instruction::LShr: OpReg = X86::SHR16rCL; break;
1521 case Instruction::AShr: OpReg = X86::SAR16rCL; break;
1522 case Instruction::Shl: OpReg = X86::SHL16rCL; break;
1529 case Instruction::LShr: OpReg = X86::SHR32rCL; break;
1530 case Instruction::AShr: OpReg = X86::SAR32rCL; break;
1531 case Instruction::Shl: OpReg = X86::SHL32rCL; break;
1538 case Instruction::LShr: OpReg = X86::SHR64rCL; break;
1539 case Instruction::AShr: OpReg = X86::SAR64rCL; break;
1540 case Instruction::Shl: OpReg = X86::SHL64rCL; break;
1567 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpReg), ResultReg)
2037 unsigned OpReg = getRegForValue(Opnd);
2038 if (OpReg == 0)
2045 .addReg(OpReg, getKillRegState(OpIsKill));
2072 unsigned OpReg = getRegForValue(I->getOperand(0));
2073 if (OpReg == 0)
2099 fastEmitInst_rr(Opcode, RC, ImplicitDefReg, true, OpReg, false);
2112 unsigned OpReg = getRegForValue(I->getOperand(0));
2113 if (OpReg == 0)
2121 MIB.addReg(OpReg);
2122 MIB.addReg(OpReg);