Lines Matching full:fp0
96 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
126 if (Reg < X86::FP0 || Reg > X86::FP6)
128 Mask |= 1 << (Reg - X86::FP0);
150 // The first entries correspond to FP0-FP6, the rest are scratch registers
291 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
292 return Reg - X86::FP0;
303 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
305 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
425 if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) {
426 DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
427 freeStackSlotAfter(I, Reg-X86::FP0);
938 unsigned R = MO.getReg() - X86::FP0;
949 // FP0.
980 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
1042 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
1152 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
1153 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1250 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
1251 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1276 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1336 unsigned Reg = MI->getOperand(0).getReg() - X86::FP0;
1392 unsigned STReg = MO.getReg() - X86::FP0;
1460 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1486 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1528 Op.getReg() >= X86::FP0 && Op.getReg() <= X86::FP6);
1561 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1668 unsigned Reg = MO.getReg() - X86::FP0;
