Lines Matching defs:Extract
1198 // Extract subvector is special because the value type
1385 // Extract subvector is special because the value type
3815 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3816 /// suitable for instruction that extract 128 or 256 bit vectors
3870 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3898 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3905 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4001 // Extract from UNDEF is UNDEF.
4005 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4314 // extract each byte of it.
5248 // Update the expected vector extract index.
6919 // If the bitcasts shift the element size, we can't extract an equivalent
8143 // We have two non-adjacent or clobbered inputs we need to extract from
8769 // them out and avoid using UNPCK{L,H} to extract the elements of V as
10360 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10362 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10377 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10379 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10399 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10403 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10414 /// Extract one bit from mask vector, like v16i1 or v8i1.
10483 // If this is a 256-bit vector result, first extract the 128-bit vector and
10484 // then extract the element from the 128-bit vector.
10522 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10524 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10617 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10671 // these bits. For example (insert (extract, 3), 2) could be matched by
12969 // Extract the LHS vectors
12974 // Extract the RHS vectors
15851 // Extract the LHS vectors
15856 // Extract the RHS vectors
15900 // Extract the odd parts.
16250 // Avoid introducing an extract element from a shuffle.
16437 // insert/extract.
16561 // Extract the two vectors
20375 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20417 // Select the input vector, guarding against out of range extract vector.
20503 // Detect mmx to i32 conversion through a v2i32 elt extract.
20542 SDNode *Extract = *UI;
20543 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20546 if (Extract->getValueType(0) != MVT::i32)
20548 if (!Extract->hasOneUse())
20550 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20551 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20553 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20558 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20560 Uses.push_back(Extract);
20568 // If 64-bit shifts are legal, use the extract-shift sequence,
20599 // Replace each use (extract) with a load of the appropriate element.
20618 SDNode *Extract = *UI;
20620 SDValue Idx = Extract->getOperand(1);
20622 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
21135 // Extract the LHS vectors
21139 // Extract the RHS vectors
22018 // bits, but can do this little dance to extract the lowest 32 bits
23464 // Extract the countS bits from the immediate so we can get the proper
23843 // Extract a subvector if necessary...
