Lines Matching defs:Size
1564 // On Darwin, -Os means optimize for size without hurting performance,
1696 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1704 if (Size >= 16 &&
1708 if (Size >= 32) {
1718 } else if (!MemcpyStrSrc && Size >= 8 &&
1726 if (Subtarget->is64Bit() && Size >= 8)
1892 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2064 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2141 /// "Dst" with size and alignment information specified by the specific
2314 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2360 // right size.
2391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2483 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2485 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2505 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2527 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2791 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2934 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2983 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3091 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3166 // achieved by reserving an area the size of the argument delta right after the
3180 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3338 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3347 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3358 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3378 if (RVLocs1.size() != RVLocs2.size())
3380 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3419 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3448 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3742 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3804 /// from position Pos and ending in Pos+Size, falls within the specified
3805 /// sequential range (Low, Low+Size]. or is undef.
3807 unsigned Pos, unsigned Size, int Low) {
3808 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4032 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4039 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4075 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4080 // extend the subvector to the size of the result vector. Make sure that
4124 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4313 // We now have to decode the element which could be any integer size and
4386 if (M >= (int)Mask.size())
4387 M -= Mask.size();
4569 assert(Zeroable.size() - Zeroable.count() > 1 &&
4763 unsigned NumElems = Elts.size();
4806 // Ensure that the input vector size for the merged loads matches the
4807 // cumulative size of the input elements.
4956 // When optimizing for size, generate up to 5 extra bytes for a broadcast
4959 // it may be detrimental to overall size. There needs to be a way to detect
4960 // that condition to know if this is truly a size win.
4968 // But override that restriction when optimizing for size.
4975 // For size optimization, also splat v2f64 and v2i64, and for size opt
5084 if (InsertIndices.size() > 1)
5123 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5772 if (Values.size() == 1) {
5883 if (Values.size() > 1 && VT.is128BitVector()) {
6062 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6073 /// an input from the second operand exists. We also assume that the size of
6074 /// mask corresponds to the size of the input vectors which isn't true in the
6078 if (M >= (int)Mask.size())
6090 int Size = Mask.size();
6091 for (int i = 0; i < Size; ++i)
6092 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6113 int Size = Mask.size();
6114 for (int i = 0; i < Size; ++i) {
6117 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6125 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6145 if (Mask.size() != ExpectedMask.size())
6148 int Size = Mask.size();
6155 for (int i = 0; i < Size; ++i)
6157 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6158 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6160 MaskBV->getOperand(Mask[i] % Size) !=
6161 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6178 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6206 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6207 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6209 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6234 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6235 if (Mask[i] >= Size) {
6236 if (Mask[i] != i + Size)
6264 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6265 if (Mask[i] >= Size)
6282 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6283 if (Mask[i] >= Size)
6299 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6333 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6337 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8));
6364 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6365 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6367 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6371 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6373 if (BlendMask[Mask[i] % Size] == -1)
6374 BlendMask[Mask[i] % Size] = Mask[i];
6375 else if (BlendMask[Mask[i] % Size] != Mask[i])
6378 PermuteMask[i] = Mask[i] % Size;
6399 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6400 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6401 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6402 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6403 if (Mask[i] >= 0 && Mask[i] < Size) {
6406 } else if (Mask[i] >= Size) {
6407 V2Mask[i] = Mask[i] - Size;
6408 BlendMask[i] = i + Size;
6449 int NumElts = Mask.size();
6468 // Get the mod-Size index and lane correct it.
6536 assert(Mask.size() <= 16 &&
6565 SmallBitVector Zeroable(Mask.size(), false);
6575 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6578 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6585 SDValue V = M < Size ? V1 : V2;
6586 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6589 SDValue Input = V.getOperand(M % Size);
6615 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6618 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6621 if (Mask[i] % Size != i)
6624 V = Mask[i] < Size ? V1 : V2;
6625 else if (V != (Mask[i] < Size ? V1 : V2))
6668 int Size = Mask.size();
6669 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6672 for (int i = 0; i < Size; i += Scale)
6681 for (int i = 0; i != Size; i += Scale) {
6686 Low + (V == V1 ? 0 : Size)))
6702 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6712 // keep doubling the size of the integer elements up to that. We can
6827 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
6878 "The input vector size must be divisible by the extended size.");
6919 // If the bitcasts shift the element size, we can't extract an equivalent
6955 [&Mask](int M) { return M >= (int)Mask.size(); }) -
6958 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6970 V2, Mask[V2Index] - Mask.size(), DAG)) {
6984 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
6987 // element size is too small to use VZEXT_MOVL to clear the high bits.
7029 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7067 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7076 int OperandSize = Mask.size() / V.getNumOperands();
7134 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7216 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7218 int Size = Mask.size();
7220 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7221 return M >= 0 && M % Size < Size / 2;
7224 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7229 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7230 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7232 for (int i = 0; i < Size; ++i) {
7241 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7247 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7248 Mask[i] % Size;
7288 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7296 PermMask.assign(Size, -1);
7297 for (int i = 0; i < Size; ++i) {
7301 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7304 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7331 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7413 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7517 assert(Mask.size() == 4 && "Unsupported mask size!");
7633 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7717 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7836 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
7852 int NumHToL = LoInputs.size() - NumLToL;
7855 int NumHToH = HiInputs.size() - NumLToH;
7894 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7896 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7898 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7906 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7907 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7908 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7909 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7910 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7925 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
7975 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7980 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8029 if (InPlaceInputs.size() == 1) {
8044 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8129 if (IncomingInputs.size() == 1) {
8140 } else if (IncomingInputs.size() == 2) {
8207 llvm_unreachable("Unhandled input size!");
8274 int Size = Mask.size();
8275 int Scale = 16 / Size;
8281 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8283 int V2Idx = Mask[i / Scale] < Size
8285 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8340 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8467 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8469 "We should only be called with masks with a power-of-2 size!");
8478 for (int i = 0, e = Mask.size(); i < e; ++i) {
8524 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8582 bool TargetLo = LoInputs.size() >= HiInputs.size();
8593 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8842 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
8880 assert(WidenedMask.size() == Mask.size() / 2 &&
8881 "Incorrect size of mask after widening the elements!");
8899 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
8900 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9028 int Size = Mask.size();
9036 if (M >= Size) {
9038 V2BroadcastIdx = M - Size;
9039 else if (M - Size != V2BroadcastIdx)
9057 int LaneSize = Size / LaneCount;
9061 for (int i = 0; i < Size; ++i)
9063 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9087 int LaneSize = Mask.size() / 2;
9093 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9094 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9095 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9101 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9103 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9106 (i / LaneSize) * LaneSize + Size));
9130 // TODO: If minimizing size and one of the inputs is a zero vector and the
9224 int Size = Mask.size();
9226 int NumLanes = Size / LaneSize;
9235 for (int i = 0; i < Size; ++i) {
9279 NewMask.resize(Size, -1);
9280 for (int i = 0; i < Size; ++i)
9296 int Size = Mask.size();
9297 for (int i = 0; i < Size; ++i)
9298 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9316 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9419 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9503 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9518 assert(RepeatedMask.size() == 4 &&
9602 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9626 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9686 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9787 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9935 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9957 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9986 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10008 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10037 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10053 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10211 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10220 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10300 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10303 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10685 // But if optimizing for size and there's a load folding opportunity,
11419 unsigned Size = SrcVT.getSizeInBits()/8;
11421 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11632 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12237 // the logic op, so it can save (~4 bytes) on code size.
12384 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12436 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12440 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12722 // if we're optimizing for size, however, as that'll allow better folding
12893 // Also promote i16 to i32 for performance / code size reason.
13438 // of 3 logic instructions for size savings and potentially speed.
13793 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13843 // Find the largest scalar type that divides the total loaded size.
13912 // the size of the target vector type.
14300 SDValue Size = Tmp2.getOperand(1);
14306 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14322 SDValue Size = Op.getOperand(1);
14347 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14356 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16841 unsigned size = 0;
16844 case MVT::i8: Reg = X86::AL; size = 1; break;
16845 case MVT::i16: Reg = X86::AX; size = 2; break;
16846 case MVT::i32: Reg = X86::EAX; size = 4; break;
16849 Reg = X86::RAX; size = 8;
16857 DAG.getTargetConstant(size, MVT::i8),
17934 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18041 // 6 ) ArgSize : Size (in bytes) of vararg type
18350 /*Size=*/16, /*Align=*/16);
18821 "Invalid Pointer Size!");
18953 "Invalid Pointer Size!");
19563 if (Mask.size() == 1) {
19656 switch (Mask.size()) {
19664 llvm_unreachable("Impossible mask size!");
19687 int Ratio = NumBytes / Mask.size();
19724 /// equivalent. In most cases, this is just an encoding size win, but
19766 "Can only combine shuffles of the same vector register size.");
19777 assert(VT.getVectorNumElements() == OpMask.size() &&
19778 "Different mask size from vector size!");
19779 assert(((RootMask.size() > OpMask.size() &&
19780 RootMask.size() % OpMask.size() == 0) ||
19781 (OpMask.size() > RootMask.size() &&
19782 OpMask.size() % RootMask.size() == 0) ||
19783 OpMask.size() == RootMask.size()) &&
19785 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
19786 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
19792 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
19798 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
19847 // so it will reduce the size of the mask to the minimal width mask which
19850 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20114 assert(Mask.size() == 4);
21257 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21770 // count is bigger than or equal to the element size.
21894 /// to the vector element size in bits.
21913 // the element size. The constant shift amount will be
22200 // Make sure the input and output size make sense
22262 // BEXTR is ((X >> imm) & (2**size-1))
22409 // have higher latencies and we are not optimizing for size.
22480 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22583 "Unexpected size for extending masked load");
22664 "Unexpected size for truncating masked store");
22666 // Accumulated smaller vector elements must be a multiple of the store size.
22775 // Accumulated smaller vector elements must be a multiple of the store size.
22815 // Bitcast the original vector into a vector of store-size units
23495 // TODO: If optimizing for size or a processor that doesn't suffer from
24046 S = S.substr(Piece.size());
24059 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24064 if (AsmPieces.size() == 3)
24086 switch (AsmPieces.size()) {
24134 if (Constraints.size() >= 2 &&
24135 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24136 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24153 if (Constraint.size() == 1) {
24480 if (Constraint.size() == 1) {
24587 if (Constraint.size() == 7 && Constraint[0] == '{' &&
