Lines Matching refs:MUL
674 setOperationAction(ISD::MUL , VT, Expand);
810 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
811 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
820 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
950 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1127 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1128 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1129 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1130 // Don't lower v32i8 because there is no 128-bit byte mul
1176 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1177 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1178 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1179 // Don't lower v32i8 because there is no 128-bit byte mul
1341 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1359 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1436 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1491 // Add/Sub/Mul with overflow operations are custom lowered.
1559 setTargetDAGCombine(ISD::MUL);
12499 case ISD::MUL:
14000 // Check for setcc([su]{add,sub,mul}o == 0).
15895 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16413 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16423 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16593 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17244 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
20312 case ISD::MUL :
21019 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21599 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23875 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23958 case ISD::MUL:
24010 case ISD::MUL:
