Lines Matching refs:SmallVectorImpl
1859 const SmallVectorImpl<ISD::OutputArg> &Outs,
1874 const SmallVectorImpl<ISD::OutputArg> &Outs,
1875 const SmallVectorImpl<SDValue> &OutVals,
2052 const SmallVectorImpl<ISD::InputArg> &Ins,
2054 SmallVectorImpl<SDValue> &InVals) const {
2114 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2128 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2190 const SmallVectorImpl<ISD::InputArg> &Ins,
2280 const SmallVectorImpl<ISD::InputArg> &Ins,
2283 SmallVectorImpl<SDValue> &InVals)
2566 SmallVectorImpl<ForwardedRegister> &Forwards =
2678 SmallVectorImpl<SDValue> &InVals) const {
2681 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2682 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2683 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3267 const SmallVectorImpl<ISD::OutputArg> &Outs,
3268 const SmallVectorImpl<SDValue> &OutVals,
3269 const SmallVectorImpl<ISD::InputArg> &Ins,
4233 SmallVectorImpl<int> &Mask, bool &IsUnary) {
6110 SmallVectorImpl<int> &RepeatedMask) {
7246 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8841 SmallVectorImpl<int> &WidenedMask) {
12385 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
15145 SmallVectorImpl<SDValue> &Results) {
15191 SmallVectorImpl<SDValue> &Results) {
17271 SmallVectorImpl<SDValue>&Results,
17853 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
17868 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20616 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
