Lines Matching full:src2
157 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
158 "imul{w}\t{$src2, $dst|$dst, $src2}",
160 (X86smul_flag GR16:$src1, GR16:$src2))], IIC_IMUL16_RR>,
162 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
163 "imul{l}\t{$src2, $dst|$dst, $src2}",
165 (X86smul_flag GR32:$src1, GR32:$src2))], IIC_IMUL32_RR>,
168 (ins GR64:$src1, GR64:$src2),
169 "imul{q}\t{$src2, $dst|$dst, $src2}",
171 (X86smul_flag GR64:$src1, GR64:$src2))], IIC_IMUL64_RR>,
178 (ins GR16:$src1, i16mem:$src2),
179 "imul{w}\t{$src2, $dst|$dst, $src2}",
181 (X86smul_flag GR16:$src1, (load addr:$src2)))],
185 (ins GR32:$src1, i32mem:$src2),
186 "imul{l}\t{$src2, $dst|$dst, $src2}",
188 (X86smul_flag GR32:$src1, (load addr:$src2)))],
192 (ins GR64:$src1, i64mem:$src2),
193 "imul{q}\t{$src2, $dst|$dst, $src2}",
195 (X86smul_flag GR64:$src1, (load addr:$src2)))],
208 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
209 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
211 (X86smul_flag GR16:$src1, imm:$src2))],
214 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
215 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
217 (X86smul_flag GR16:$src1, i16immSExt8:$src2))],
220 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
221 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
223 (X86smul_flag GR32:$src1, imm:$src2))],
226 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
227 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 (X86smul_flag GR32:$src1, i32immSExt8:$src2))],
232 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
233 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
235 (X86smul_flag GR64:$src1, i64immSExt32:$src2))],
238 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
239 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
241 (X86smul_flag GR64:$src1, i64immSExt8:$src2))],
248 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
249 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 (X86smul_flag (load addr:$src1), imm:$src2))],
255 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
256 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
259 i16immSExt8:$src2))], IIC_IMUL16_RMI>,
262 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
263 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
265 (X86smul_flag (load addr:$src1), imm:$src2))],
268 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
269 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
272 i32immSExt8:$src2))],
275 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
276 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
279 i64immSExt32:$src2))],
282 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
283 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
286 i64immSExt8:$src2))],
658 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
659 mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
668 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
677 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
686 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
694 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
695 mnemonic, "{$src2, $dst|$dst, $src2}", [], itin>,
710 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
711 mnemonic, "{$src2, $src1|$src1, $src2}", [], IIC_BIN_NONMEM>,
724 (ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
725 mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
733 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
740 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
747 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
754 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2),
762 (ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2),
763 mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
773 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
780 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
786 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2,
794 (ins typeinfo.RegClass:$src1, typeinfo.Imm8Operand:$src2),
795 mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>,
805 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
812 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
819 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2,
1264 def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1265 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1266 [(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))],
1268 def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1269 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1271 (X86and_flag (not RC:$src1), (ld_frag addr:$src2)))], IIC_BIN_MEM>,
1281 def : Pat<(and (not GR32:$src1), GR32:$src2),
1282 (ANDN32rr GR32:$src1, GR32:$src2)>;
1283 def : Pat<(and (not GR64:$src1), GR64:$src2),
1284 (ANDN64rr GR64:$src1, GR64:$src2)>;
1285 def : Pat<(and (not GR32:$src1), (loadi32 addr:$src2)),
1286 (ANDN32rm GR32:$src1, addr:$src2)>;
1287 def : Pat<(and (not GR64:$src1), (loadi64 addr:$src2)),
1288 (ANDN64rm GR64:$src1, addr:$src2)>;
