Lines Matching full:src2
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
35 "shl{b}\t{$src2, $dst|$dst, $src2}",
36 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
40 "shl{w}\t{$src2, $dst|$dst, $src2}",
41 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>,
43 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
44 "shl{l}\t{$src2, $dst|$dst, $src2}",
45 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>,
48 (ins GR64:$src1, i8imm:$src2),
49 "shl{q}\t{$src2, $dst|$dst, $src2}",
50 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
140 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
141 "shr{b}\t{$src2, $dst|$dst, $src2}",
142 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
143 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
144 "shr{w}\t{$src2, $dst|$dst, $src2}",
145 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))],
147 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
148 "shr{l}\t{$src2, $dst|$dst, $src2}",
149 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],
151 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
152 "shr{q}\t{$src2, $dst|$dst, $src2}",
153 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>;
244 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
245 "sar{b}\t{$src2, $dst|$dst, $src2}",
246 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))],
248 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
249 "sar{w}\t{$src2, $dst|$dst, $src2}",
250 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))],
252 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
253 "sar{l}\t{$src2, $dst|$dst, $src2}",
254 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
257 (ins GR64:$src1, i8imm:$src2),
258 "sar{q}\t{$src2, $dst|$dst, $src2}",
259 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))],
485 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
486 "rol{b}\t{$src2, $dst|$dst, $src2}",
487 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
488 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
489 "rol{w}\t{$src2, $dst|$dst, $src2}",
490 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))],
492 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
493 "rol{l}\t{$src2, $dst|$dst, $src2}",
494 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
497 (ins GR64:$src1, i8imm:$src2),
498 "rol{q}\t{$src2, $dst|$dst, $src2}",
499 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))],
592 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
593 "ror{b}\t{$src2, $dst|$dst, $src2}",
594 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
595 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
596 "ror{w}\t{$src2, $dst|$dst, $src2}",
597 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))],
599 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
600 "ror{l}\t{$src2, $dst|$dst, $src2}",
601 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))],
604 (ins GR64:$src1, i8imm:$src2),
605 "ror{q}\t{$src2, $dst|$dst, $src2}",
606 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))],
692 (ins GR16:$src1, GR16:$src2),
693 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
694 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))],
698 (ins GR16:$src1, GR16:$src2),
699 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
700 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))],
704 (ins GR32:$src1, GR32:$src2),
705 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
706 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],
709 (ins GR32:$src1, GR32:$src2),
710 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
711 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],
714 (ins GR64:$src1, GR64:$src2),
715 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
716 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))],
720 (ins GR64:$src1, GR64:$src2),
721 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
722 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))],
730 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
731 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
732 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
737 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
738 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
739 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
744 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
745 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
746 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
751 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
752 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
753 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
758 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
759 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
760 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
765 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
766 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
767 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
775 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
776 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
777 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
779 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
780 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
781 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
784 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
785 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
786 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
788 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
789 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
790 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
793 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
794 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
795 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
797 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
798 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
799 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
804 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
805 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
806 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
811 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
812 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
813 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
819 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
820 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
821 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
826 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
827 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
828 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
834 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
835 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
836 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
841 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
842 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
843 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
863 def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2),
864 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
868 (ins x86memop:$src1, i8imm:$src2),
869 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
876 def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
877 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
880 def rm : I<0xF7, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
881 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
929 def : Pat<(sra GR32:$src1, GR8:$src2),
932 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
933 def : Pat<(sra GR64:$src1, GR8:$src2),
936 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
938 def : Pat<(srl GR32:$src1, GR8:$src2),
941 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
942 def : Pat<(srl GR64:$src1, GR8:$src2),
945 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
947 def : Pat<(shl GR32:$src1, GR8:$src2),
950 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
951 def : Pat<(shl GR64:$src1, GR8:$src2),
954 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
