Lines Matching full:src2
88 (ins VR128:$src1, VR128:$src2),
89 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
90 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2))]>, XOP_4VOp3;
92 (ins VR128:$src1, i128mem:$src2),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
95 (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2))))]>,
98 (ins i128mem:$src1, VR128:$src2),
99 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
101 (Int (bitconvert (loadv2i64 addr:$src1)), VR128:$src2))]>,
122 (ins VR128:$src1, i8imm:$src2),
123 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
124 [(set VR128:$dst, (Int VR128:$src1, imm:$src2))]>, XOP;
126 (ins i128mem:$src1, i8imm:$src2),
127 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
129 (Int (bitconvert (loadv2i64 addr:$src1)), imm:$src2))]>, XOP;
143 (ins VR128:$src1, VR128:$src2, VR128:$src3),
145 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
147 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_4V, VEX_I8IMM;
149 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
151 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
153 (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
176 (ins VR128:$src1, VR128:$src2, XOPCC:$cc),
178 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
179 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, i8immZExt3:$cc))]>,
182 (ins VR128:$src1, i128mem:$src2, XOPCC:$cc),
184 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
186 (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
190 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
192 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
196 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
198 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
217 (ins VR128:$src1, VR128:$src2, VR128:$src3),
219 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
220 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, VR128:$src3))]>,
223 (ins VR128:$src1, VR128:$src2, i128mem:$src3),
225 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
227 (Int VR128:$src1, VR128:$src2,
231 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
233 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
235 (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
247 (ins VR256:$src1, VR256:$src2, VR256:$src3),
249 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
250 [(set VR256:$dst, (Int VR256:$src1, VR256:$src2, VR256:$src3))]>,
253 (ins VR256:$src1, VR256:$src2, i256mem:$src3),
255 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
257 (Int VR256:$src1, VR256:$src2,
261 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
263 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
265 (Int VR256:$src1, (bitconvert (loadv4i64 addr:$src2)),
276 (ins VR128:$src1, VR128:$src2, VR128:$src3, i8imm:$src4),
278 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
280 (Int128 VR128:$src1, VR128:$src2, VR128:$src3, imm:$src4))]>;
282 (ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4),
284 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
286 (Int128 VR128:$src1, VR128:$src2, (ld_128 addr:$src3), imm:$src4))]>,
289 (ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4),
291 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
293 (Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>;
295 (ins VR256:$src1, VR256:$src2, VR256:$src3, i8imm:$src4),
297 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
299 (Int256 VR256:$src1, VR256:$src2, VR256:$src3, imm:$src4))]>, VEX_L;
301 (ins VR256:$src1, VR256:$src2, f256mem:$src3, i8imm:$src4),
303 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
305 (Int256 VR256:$src1, VR256:$src2, (ld_256 addr:$src3), imm:$src4))]>,
308 (ins VR256:$src1, f256mem:$src2, VR256:$src3, i8imm:$src4),
310 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
312 (Int256 VR256:$src1, (ld_256 addr:$src2), VR256:$src3, imm:$src4))]>,
