Lines Matching full:src4
276 (ins VR128:$src1, VR128:$src2, VR128:$src3, i8imm:$src4),
278 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
280 (Int128 VR128:$src1, VR128:$src2, VR128:$src3, imm:$src4))]>;
282 (ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4),
284 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
286 (Int128 VR128:$src1, VR128:$src2, (ld_128 addr:$src3), imm:$src4))]>,
289 (ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4),
291 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
293 (Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>;
295 (ins VR256:$src1, VR256:$src2, VR256:$src3, i8imm:$src4),
297 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
299 (Int256 VR256:$src1, VR256:$src2, VR256:$src3, imm:$src4))]>, VEX_L;
301 (ins VR256:$src1, VR256:$src2, f256mem:$src3, i8imm:$src4),
303 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
305 (Int256 VR256:$src1, VR256:$src2, (ld_256 addr:$src3), imm:$src4))]>,
308 (ins VR256:$src1, f256mem:$src2, VR256:$src3, i8imm:$src4),
310 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
312 (Int256 VR256:$src1, (ld_256 addr:$src2), VR256:$src3, imm:$src4))]>,
