Lines Matching full:sqshrn
743 ; CHECK: sqshrn {{s[0-9]+}}, d0, #1
744 %tmp = call i32 @llvm.aarch64.neon.sqshrn.i32(i64 %A, i32 1)
750 ;CHECK: sqshrn.8b v0, {{v[0-9]+}}, #1
752 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1)
758 ;CHECK: sqshrn.4h v0, {{v[0-9]+}}, #1
760 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1)
766 ;CHECK: sqshrn.2s v0, {{v[0-9]+}}, #1
768 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1)
778 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1)
788 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1)
798 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1)
803 declare i32 @llvm.aarch64.neon.sqshrn.i32(i64, i32) nounwind readnone
804 declare <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16>, i32) nounwind readnone
805 declare <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32>, i32) nounwind readnone
806 declare <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64>, i32) nounwind readnone
