Lines Matching full:ands
15 ANDS r0, r2, r1 // Must be wide - 3 distinct registers
16 ANDS r2, r2, r1 // Should choose narrow
17 ANDS r2, r1, r2 // Should choose narrow - commutative
18 ANDS.W r0, r0, r1 // Explicitly wide
19 ANDS.W r3, r1, r3
21 ANDS r7, r7, r1 // Should use narrow
22 ANDS r7, r1, r7 // Commutative
23 ANDS r8, r1, r8 // high registers so must use wide encoding
24 ANDS r8, r8, r1
25 ANDS r0, r8, r0
26 ANDS r1, r1, r8
27 ANDS r2, r2, r1, lsl #1 // Must use wide - shifted register
28 ANDS r0, r1, r0, lsr #1
29 // CHECK: ands.w r0, r2, r1 @ encoding: [0x12,0xea,0x01,0x00]
30 // CHECK: ands r2, r1 @ encoding: [0x0a,0x40]
31 // CHECK: ands r2, r1 @ encoding: [0x0a,0x40]
32 // CHECK: ands.w r0, r0, r1 @ encoding: [0x10,0xea,0x01,0x00]
33 // CHECK: ands.w r3, r1, r3 @ encoding: [0x11,0xea,0x03,0x03]
35 // CHECK: ands r7, r1 @ encoding: [0x0f,0x40]
36 // CHECK: ands r7, r1 @ encoding: [0x0f,0x40]
37 // CHECK: ands.w r8, r1, r8 @ encoding: [0x11,0xea,0x08,0x08]
38 // CHECK: ands.w r8, r8, r1 @ encoding: [0x18,0xea,0x01,0x08]
39 // CHECK: ands.w r0, r8, r0 @ encoding: [0x18,0xea,0x00,0x00]
40 // CHECK: ands.w r1, r1, r8 @ encoding: [0x11,0xea,0x08,0x01]
41 // CHECK: ands.w r2, r2, r1, lsl #1 @ encoding: [0x12,0xea,0x41,0x02]
42 // CHECK: ands.w r0, r1, r0, lsr #1 @ encoding: [0x11,0xea,0x50,0x00]
