Lines Matching full:processor
34 // Each processor has a SchedClassDesc table with an entry for each SchedClass.
226 // Gather and sort processor information
228 Records.getAllDerivedDefinitions("Processor");
231 // Begin processor table
236 // For each processor
238 // Next processor
239 Record *Processor = ProcessorList[i];
241 const std::string &Name = Processor->getValueAsString("Name");
243 Processor->getValueAsListOfDefs("Features");
248 << "\"Select the " << Name << " processor\", ";
268 // End processor table
369 // Multiple processor models may share an itinerary record. Emit it once.
434 // If this processor defines no itineraries, then leave the itinerary list
536 // EmitProcessorData - Generate data for processor itineraries that were
538 // Itineraries for each processor. The Itinerary lists are indexed on
545 // Multiple processor models may share an itinerary record. Emit it once.
548 // For each processor's machine model
558 // Get processor itinerary name
561 // Get the itinerary list for the processor.
573 // Begin processor itinerary table
590 // End processor itinerary table
597 // value defined in the C++ header. The Record is null if the processor does not
657 // Find the WriteRes Record that defines processor resources for this
663 // specifies a set of processor resources.
679 "defined for processor " + ProcModel.ModelName +
686 // Check this processor's list of write resources.
696 "SchedWrite and its alias on processor " +
702 // TODO: If ProcModel has a base model (previous generation processor),
706 std::string("Processor does not define resources for ")
712 /// Find the ReadAdvance record for the given SchedRead on this processor or
720 // Check this processor's list of aliases for SchedRead.
733 "defined for processor " + ProcModel.ModelName +
740 // Check this processor's ReadAdvanceList.
750 "SchedRead and its alias on processor " +
756 // TODO: If ProcModel has a base model (previous generation processor),
760 std::string("Processor does not define resources for ")
766 // Expand an explicit list of processor resources into a full list of implied
785 PrintFatalError(SubDef->getLoc(), "Processor resource group "
816 // Generate the SchedClass table for this processor and update global
817 // tables. Must be called for each processor in order.
860 // Determine if the SchedClass is actually reachable on this processor. If
861 // not don't try to locate the processor resources, it will fail.
892 // Check this processor's itinerary class resources.
1126 // Emit a SchedClass table for each processor.
1171 // For each processor model.
1174 // Emit processor resource table.
1181 // Begin processor itinerary properties
1199 OS << " " << PI->Index << ", // Processor ID\n";
1219 // Gather and sort processor information
1221 Records.getAllDerivedDefinitions("Processor");
1224 // Begin processor table
1230 // For each processor
1232 // Next processor
1233 Record *Processor = ProcessorList[i];
1235 const std::string &Name = Processor->getValueAsString("Name");
1237 SchedModels.getModelForProc(Processor).ModelName;
1248 // End processor table
1281 // Emit the processor machine model
1283 // Emit the processor lookup data
