Lines Matching refs:inst1
382 * first halfword is INST1. */
385 thumb_insn_size (unsigned short inst1)
387 if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
397 uint16_t inst1;
399 if (proc_read_16(proc, pc, &inst1) < 0
411 if ((inst1 & 0xff00) == 0xbd00) { /* pop {rlist, pc} */
414 const unsigned offset = bitcount(BITS(inst1, 0, 7)) * 4;
423 } else if ((inst1 & 0xf000) == 0xd000) { /* conditional branch */
424 const unsigned long cond = BITS(inst1, 8, 11);
426 next_pcs[nr++] = pc + (SBITS(inst1, 0, 7) << 1);
430 } else if ((inst1 & 0xf800) == 0xe000) { /* unconditional branch */
431 next_pcs[nr++] = pc + (SBITS(inst1, 0, 10) << 1);
432 } else if (thumb_insn_size(inst1) == 4) { /* 32-bit instruction */
437 if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000) {
444 const int imm1 = SBITS(inst1, 0, 10);
461 } else if (inst1 == 0xf3de
473 && (inst1 & 0x0380) != 0x0380) {
475 const int sign = SBITS(inst1, 10, 10);
476 const unsigned imm1 = BITS(inst1, 0, 5);
485 if (BITS(inst1, 6, 9) == COND_ALWAYS)
488 } else if ((inst1 & 0xfe50) == 0xe810) {
491 const enum arm_register rn = BITS(inst1, 0, 3);
493 if (BIT(inst1, 7) && !BIT(inst1, 8)) {
498 } else if (!BIT(inst1, 7) && BIT(inst1, 8)) {
503 } else if (BIT(inst1, 7) && BIT(inst1, 8)) {
506 } else if (!BIT(inst1, 7) && !BIT(inst1, 8)) {
524 } else if ((inst1 & 0xffef) == 0xea4f
533 } else if ((inst1 & 0xff70) == 0xf850
536 const enum arm_register rn = BITS(inst1, 0, 3);
544 if (BIT(inst1, 7))
548 } else if (BIT(inst1, 7)) {
577 } else if ((inst1 & 0xfff0) == 0xe8d0
580 const enum arm_register tbl_reg = BITS(inst1, 0, 3);
603 } else if ((inst1 & 0xfff0) == 0xe8d0
606 const enum arm_register tbl_reg = BITS(inst1, 0, 3);
634 next_pcs[nr++] = pc + thumb_insn_size(inst1);
