Lines Matching refs:si_pm4_set_reg
67 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
70 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
78 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
79 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
89 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
92 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
170 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
183 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
184 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
185 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
188 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, 0);
192 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
193 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
203 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
206 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
209 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
259 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
260 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
261 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
262 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
264 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
265 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
267 si_pm4_set_reg(pm4, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
268 si_pm4_set_reg(pm4, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
275 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
280 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
283 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
285 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
289 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL, rctx->pa_cl_clip_cntl
308 si_pm4_set_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
353 si_pm4_set_reg(pm4, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp);
467 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
469 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
