Lines Matching refs:CP_PACKET0
163 return CP_PACKET0(packet[id].start, packet[id].len - 1);
243 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
245 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
254 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
372 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
376 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
379 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
383 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
385 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
390 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
393 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
403 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
405 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
474 OUT_BATCH(CP_PACKET0(RADEON_PP_TXFILTER_0 + (24 * i), 1));
478 OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0));
495 OUT_BATCH(CP_PACKET0(RADEON_PP_TXCBLEND_0 + (i * 24), 1));
497 OUT_BATCH(CP_PACKET0(RADEON_PP_BORDER_COLOR_0 + (i * 4), 0));
644 rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0);
918 rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0);
