Lines Matching defs:pc
241 Instr* pc = reinterpret_cast<Instr*>(pc_);
244 *(pc + i) = *(instr + i);
252 // Patch the code at the current PC with a call to the target address.
342 rm_ = (am == Offset) ? pc : sp;
410 // ldr rd, [pc, #offset]
419 // vldr dd, [pc, #offset]
687 // ldr<cond> <Rd>, [pc +/- offset_12].
711 // vldr<cond> <Dd>, [pc +/- offset_10].
1121 Register target = rd.code() == pc.code() ? ip : rd;
1144 Register target = rd.code() == pc.code() ? ip : rd;
1159 ldr(rd, MemOperand(FLAG_enable_ool_constant_pool ? pp : pc, 0), cond);
1180 // condition code), then replace it with a 'ldr rd, [pc]'.
1197 DCHECK(!rn.is(pc) && !rd.is(pc) && !x.rm_.is(pc) && !x.rs_.is(pc));
1201 if (rn.is(pc) || x.rm_.is(pc)) {
1202 // Block constant pool emission for one instruction after reading pc.
1232 DCHECK(!x.rm_.is(pc));
1235 DCHECK((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback
1271 DCHECK((am & (P|W)) == P || !x.rm_.is(pc)); // no pc index with writeback
1274 DCHECK((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback
1282 DCHECK(!rn.is(pc));
1301 DCHECK((am & (P|W)) == P || !x.rn_.is(pc)); // no pc base with writeback
1328 // be emitted at the pc offset recorded by the label.
1369 DCHECK(!target.is(pc));
1376 DCHECK(!target.is(pc)); // use of pc is actually allowed, but discouraged
1465 if (dst.is(pc)) {
1541 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
1549 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
1558 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
1567 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
1576 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
1588 DCHECK(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1601 DCHECK(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1614 DCHECK(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1627 DCHECK(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1637 DCHECK(!dst.is(pc) && !src.is(pc));
1652 DCHECK(!dst.is(pc) && !src.rm_.is(pc));
1680 DCHECK(!dst.is(pc) && !src.is(pc));
1700 DCHECK(!dst.is(pc) && !src.is(pc));
1715 DCHECK(!dst.is(pc));
1734 DCHECK(!dst.is(pc) && !src.is(pc));
1750 DCHECK(!dst.is(pc));
1751 DCHECK(!src1.is(pc));
1752 DCHECK(!src2.rm().is(pc));
1769 DCHECK(!dst.is(pc));
1770 DCHECK(!src1.is(pc));
1771 DCHECK(!src2.rm().is(pc));
1788 DCHECK(!dst.is(pc));
1789 DCHECK(!src.rm().is(pc));
1811 DCHECK(!dst.is(pc));
1812 DCHECK(!src1.is(pc));
1813 DCHECK(!src2.rm().is(pc));
1834 DCHECK(!dst.is(pc));
1835 DCHECK(!src.rm().is(pc));
1852 DCHECK(!dst.is(pc));
1883 if (dst.is(pc)) {
1976 // Emit the constant pool after a function return implemented by ldm ..{..pc}.
1977 if (cond == al && (dst & pc.bit()) != 0) {
1981 // at the pc of the ldm instruction by a mov lr, pc instruction; if this is
2350 DCHECK(!base.is(pc));
2371 DCHECK(!base.is(pc));
2391 DCHECK(!base.is(pc));
2411 DCHECK(!base.is(pc));
2522 vldr(dst, MemOperand(FLAG_enable_ool_constant_pool ? pp : pc, 0));
2629 DCHECK(!src1.is(pc) && !src2.is(pc));
2645 DCHECK(!dst1.is(pc) && !dst2.is(pc));
2660 DCHECK(!src.is(pc));
2674 DCHECK(!dst.is(pc));
3129 DCHECK(0 <= type && type <= 14); // mov pc, pc isn't a nop.
3186 DCHECK(0 <= type && type <= 14); // mov pc, pc isn't a nop.
3278 // None of our relocation types are pc relative pointing outside the code
3279 // buffer nor pc absolute pointing inside the code buffer, so there is no need
3288 rinfo.set_pc(rinfo.pc() + pc_delta);
3294 rinfo.set_pc(rinfo.pc() + pc_delta);
3347 RelocInfo reloc_info_with_ast_id(rinfo.pc(),
3518 Instr instr = instr_at(rinfo.pc());
3519 // Instruction to patch must be 'vldr rd, [pc, #offset]' with offset == 0.
3523 int delta = pc_ - rinfo.pc() - kPcLoadDelta;
3533 Instr instr2 = instr_at(rinfo2.pc());
3536 delta += rinfo2.pc() - rinfo.pc();
3541 instr_at_put(rinfo.pc(), SetVldrDRegisterImmediateOffset(instr, delta));
3559 Instr instr = instr_at(rinfo.pc());
3566 int delta = pc_ - rinfo.pc() - kPcLoadDelta;
3569 // ldr rd, [pc, #0]
3580 Instr instr2 = instr_at(rinfo2.pc());
3583 delta += rinfo2.pc() - rinfo.pc();
3591 instr_at_put(rinfo.pc(), SetLdrRegisterImmediateOffset(instr, delta));
3704 entry->rinfo_.set_pc(entry->rinfo_.pc() + pc_delta);
3781 Instr instr = assm->instr_at(rinfo.pc());
3785 Instr next_instr = assm->instr_at(rinfo.pc() + Assembler::kInstrSize);
3791 rinfo.pc(), Assembler::PatchMovwImmediate(instr, offset & 0xffff));
3793 rinfo.pc() + Assembler::kInstrSize,
3797 Instr instr_2 = assm->instr_at(rinfo.pc() + Assembler::kInstrSize);
3798 Instr instr_3 = assm->instr_at(rinfo.pc() + 2 * Assembler::kInstrSize);
3799 Instr instr_4 = assm->instr_at(rinfo.pc() + 3 * Assembler::kInstrSize);
3812 rinfo.pc(), Assembler::PatchShiftImm(instr, (offset & kImm8Mask)));
3814 rinfo.pc() + Assembler::kInstrSize,
3817 rinfo.pc() + 2 * Assembler::kInstrSize,
3820 rinfo.pc() + 3 * Assembler::kInstrSize,
3828 assm->instr_at_put(rinfo.pc(), Assembler::SetVldrDRegisterImmediateOffset(
3836 rinfo.pc(), Assembler::SetLdrRegisterImmediateOffset(instr, offset));
