Lines Matching full:destination
721 InstructionOperand* destination) {
723 // Dispatch on the source and destination operand kinds. Not all
726 DCHECK(destination->IsRegister() || destination->IsStackSlot());
728 if (destination->IsRegister()) {
729 __ Mov(g.ToRegister(destination), src);
731 __ Str(src, g.ToMemOperand(destination, masm()));
735 DCHECK(destination->IsRegister() || destination->IsStackSlot());
736 if (destination->IsRegister()) {
737 __ Ldr(g.ToRegister(destination), src);
742 __ Str(temp, g.ToMemOperand(destination, masm()));
746 if (destination->IsRegister() || destination->IsStackSlot()) {
748 Register dst = destination->IsRegister() ? g.ToRegister(destination)
756 if (destination->IsStackSlot()) {
757 __ Str(dst, g.ToMemOperand(destination, masm()));
759 } else if (destination->IsDoubleRegister()) {
760 FPRegister result = g.ToDoubleRegister(destination);
763 DCHECK(destination->IsDoubleStackSlot());
767 __ Str(temp, g.ToMemOperand(destination, masm()));
771 if (destination->IsDoubleRegister()) {
772 FPRegister dst = g.ToDoubleRegister(destination);
775 DCHECK(destination->IsDoubleStackSlot());
776 __ Str(src, g.ToMemOperand(destination, masm()));
779 DCHECK(destination->IsDoubleRegister() || destination->IsDoubleStackSlot());
781 if (destination->IsDoubleRegister()) {
782 __ Ldr(g.ToDoubleRegister(destination), src);
787 __ Str(temp, g.ToMemOperand(destination, masm()));
796 InstructionOperand* destination) {
798 // Dispatch on the source and destination operand kinds. Not all
805 if (destination->IsRegister()) {
806 Register dst = g.ToRegister(destination);
811 DCHECK(destination->IsStackSlot());
812 MemOperand dst = g.ToMemOperand(destination, masm());
822 MemOperand dst = g.ToMemOperand(destination, masm());
831 if (destination->IsDoubleRegister()) {
832 FPRegister dst = g.ToDoubleRegister(destination);
837 DCHECK(destination->IsDoubleStackSlot());
838 MemOperand dst = g.ToMemOperand(destination, masm());
