Lines Matching refs:rs
343 Register rs;
344 rs.code_ = (instr & kRsFieldMask) >> kRsShift;
345 return rs;
851 Register rs,
856 DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));
857 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
864 Register rs,
869 DCHECK(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb));
870 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
930 Register rs,
933 DCHECK(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j)));
934 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
941 Register rs,
944 DCHECK(rs.is_valid() && (is_int16(j) || is_uint16(j)));
945 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask);
951 Register rs,
954 DCHECK(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j)));
955 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift)
1153 void Assembler::beq(Register rs, Register rt, int16_t offset) {
1155 rs, rt, offset);
1160 void Assembler::bgez(Register rs, int16_t offset) {
1162 GenInstrImmediate(REGIMM, rs, BGEZ, offset);
1174 void Assembler::bgeuc(Register rs, Register rt, int16_t offset) {
1176 DCHECK(!(rs.is(zero_reg)));
1178 DCHECK(rs.code() != rt.code());
1179 GenInstrImmediate(BLEZ, rs, rt, offset);
1183 void Assembler::bgec(Register rs, Register rt, int16_t offset) {
1185 DCHECK(!(rs.is(zero_reg)));
1187 DCHECK(rs.code() != rt.code());
1188 GenInstrImmediate(BLEZL, rs, rt, offset);
1192 void Assembler::bgezal(Register rs, int16_t offset) {
1193 DCHECK(kArchVariant != kMips64r6 || rs.is(zero_reg));
1196 GenInstrImmediate(REGIMM, rs, BGEZAL, offset);
1201 void Assembler::bgtz(Register rs, int16_t offset) {
1203 GenInstrImmediate(BGTZ, rs, zero_reg, offset);
1215 void Assembler::blez(Register rs, int16_t offset) {
1217 GenInstrImmediate(BLEZ, rs, zero_reg, offset);
1236 void Assembler::bltuc(Register rs, Register rt, int16_t offset) {
1238 DCHECK(!(rs.is(zero_reg)));
1240 DCHECK(rs.code() != rt.code());
1241 GenInstrImmediate(BGTZ, rs, rt, offset);
1245 void Assembler::bltc(Register rs, Register rt, int16_t offset) {
1247 DCHECK(!(rs.is(zero_reg)));
1249 DCHECK(rs.code() != rt.code());
1250 GenInstrImmediate(BGTZL, rs, rt, offset);
1254 void Assembler::bltz(Register rs, int16_t offset) {
1256 GenInstrImmediate(REGIMM, rs, BLTZ, offset);
1261 void Assembler::bltzal(Register rs, int16_t offset) {
1262 DCHECK(kArchVariant != kMips64r6 || rs.is(zero_reg));
1265 GenInstrImmediate(REGIMM, rs, BLTZAL, offset);
1270 void Assembler::bne(Register rs, Register rt, int16_t offset) {
1272 GenInstrImmediate(BNE, rs, rt, offset);
1277 void Assembler::bovc(Register rs, Register rt, int16_t offset) {
1279 DCHECK(!(rs.is(zero_reg)));
1280 DCHECK(rs.code() >= rt.code());
1281 GenInstrImmediate(ADDI, rs, rt, offset);
1285 void Assembler::bnvc(Register rs, Register rt, int16_t offset) {
1287 DCHECK(!(rs.is(zero_reg)));
1288 DCHECK(rs.code() >= rt.code());
1289 GenInstrImmediate(DADDI, rs, rt, offset);
1307 void Assembler::bgezall(Register rs, int16_t offset) {
1309 DCHECK(!(rs.is(zero_reg)));
1310 GenInstrImmediate(REGIMM, rs, BGEZALL, offset);
1342 void Assembler::beqc(Register rs, Register rt, int16_t offset) {
1344 DCHECK(rs.code() < rt.code());
1345 GenInstrImmediate(ADDI, rs, rt, offset);
1349 void Assembler::beqzc(Register rs, int32_t offset) {
1351 DCHECK(!(rs.is(zero_reg)));
1352 Instr instr = BEQZC | (rs.code() << kRsShift) | offset;
1357 void Assembler::bnec(Register rs, Register rt, int16_t offset) {
1359 DCHECK(rs.code() < rt.code());
1360 GenInstrImmediate(DADDI, rs, rt, offset);
1364 void Assembler::bnezc(Register rs, int32_t offset) {
1366 DCHECK(!(rs.is(zero_reg)));
1367 Instr instr = BNEZC | (rs.code() << kRsShift) | offset;
1384 void Assembler::jr(Register rs) {
1387 if (rs.is(ra)) {
1390 GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR);
1393 jalr(rs, zero_reg);
1411 void Assembler::jalr(Register rs, Register rd) {
1414 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR);
1419 void Assembler::j_or_jr(int64_t target, Register rs) {
1432 void Assembler::jal_or_jalr(int64_t target, Register rs) {
1449 void Assembler::addu(Register rd, Register rs, Register rt) {
1450 GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU);
1454 void Assembler::addiu(Register rd, Register rs, int32_t j) {
1455 GenInstrImmediate(ADDIU, rs, rd, j);
1459 void Assembler::subu(Register rd, Register rs, Register rt) {
1460 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU);
1464 void Assembler::mul(Register rd, Register rs, Register rt) {
1466 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH);
1468 GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL);
1473 void Assembler::muh(Register rd, Register rs, Register rt) {
1475 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH);
1479 void Assembler::mulu(Register rd, Register rs, Register rt) {
1481 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH_U);
1485 void Assembler::muhu(Register rd, Register rs, Register rt) {
1487 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH_U);
1491 void Assembler::dmul(Register rd, Register rs, Register rt) {
1493 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH);
1497 void Assembler::dmuh(Register rd, Register rs, Register rt) {
1499 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH);
1503 void Assembler::dmulu(Register rd, Register rs, Register rt) {
1505 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH_U);
1509 void Assembler::dmuhu(Register rd, Register rs, Register rt) {
1511 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH_U);
1515 void Assembler::mult(Register rs, Register rt) {
1517 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULT);
1521 void Assembler::multu(Register rs, Register rt) {
1523 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU);
1527 void Assembler::daddiu(Register rd, Register rs, int32_t j) {
1528 GenInstrImmediate(DADDIU, rs, rd, j);
1532 void Assembler::div(Register rs, Register rt) {
1533 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIV);
1537 void Assembler::div(Register rd, Register rs, Register rt) {
1539 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD);
1543 void Assembler::mod(Register rd, Register rs, Register rt) {
1545 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD);
1549 void Assembler::divu(Register rs, Register rt) {
1550 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU);
1554 void Assembler::divu(Register rd, Register rs, Register rt) {
1556 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U);
1560 void Assembler::modu(Register rd, Register rs, Register rt) {
1562 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD_U);
1566 void Assembler::daddu(Register rd, Register rs, Register rt) {
1567 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DADDU);
1571 void Assembler::dsubu(Register rd, Register rs, Register rt) {
1572 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSUBU);
1576 void Assembler::dmult(Register rs, Register rt) {
1577 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DMULT);
1581 void Assembler::dmultu(Register rs, Register rt) {
1582 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DMULTU);
1586 void Assembler::ddiv(Register rs, Register rt) {
1587 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DDIV);
1591 void Assembler::ddiv(Register rd, Register rs, Register rt) {
1593 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD);
1597 void Assembler::dmod(Register rd, Register rs, Register rt) {
1599 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD);
1603 void Assembler::ddivu(Register rs, Register rt) {
1604 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DDIVU);
1608 void Assembler::ddivu(Register rd, Register rs, Register rt) {
1610 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD_U);
1614 void Assembler::dmodu(Register rd, Register rs, Register rt) {
1616 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD_U);
1622 void Assembler::and_(Register rd, Register rs, Register rt) {
1623 GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND);
1627 void Assembler::andi(Register rt, Register rs, int32_t j) {
1629 GenInstrImmediate(ANDI, rs, rt, j);
1633 void Assembler::or_(Register rd, Register rs, Register rt) {
1634 GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR);
1638 void Assembler::ori(Register rt, Register rs, int32_t j) {
1640 GenInstrImmediate(ORI, rs, rt, j);
1644 void Assembler::xor_(Register rd, Register rs, Register rt) {
1645 GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR);
1649 void Assembler::xori(Register rt, Register rs, int32_t j) {
1651 GenInstrImmediate(XORI, rs, rt, j);
1655 void Assembler::nor(Register rd, Register rs, Register rt) {
1656 GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR);
1674 void Assembler::sllv(Register rd, Register rt, Register rs) {
1675 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV);
1684 void Assembler::srlv(Register rd, Register rt, Register rs) {
1685 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV);
1694 void Assembler::srav(Register rd, Register rt, Register rs) {
1695 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV);
1709 void Assembler::rotrv(Register rd, Register rt, Register rs) {
1711 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() );
1713 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift)
1724 void Assembler::dsllv(Register rd, Register rt, Register rs) {
1725 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSLLV);
1734 void Assembler::dsrlv(Register rd, Register rt, Register rs) {
1735 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRLV);
1747 void Assembler::drotrv(Register rd, Register rt, Register rs) {
1748 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() );
1749 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift)
1760 void Assembler::dsrav(Register rd, Register rt, Register rs) {
1761 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRAV);
1793 void Assembler::lb(Register rd, const MemOperand& rs) {
1794 if (is_int16(rs.offset_)) {
1795 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_);
1797 LoadRegPlusOffsetToAt(rs);
1803 void Assembler::lbu(Register rd, const MemOperand& rs) {
1804 if (is_int16(rs.offset_)) {
1805 GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_);
1807 LoadRegPlusOffsetToAt(rs);
1813 void Assembler::lh(Register rd, const MemOperand& rs) {
1814 if (is_int16(rs.offset_)) {
1815 GenInstrImmediate(LH, rs.rm(), rd, rs.offset_);
1817 LoadRegPlusOffsetToAt(rs);
1823 void Assembler::lhu(Register rd, const MemOperand& rs) {
1824 if (is_int16(rs.offset_)) {
1825 GenInstrImmediate(LHU, rs.rm(), rd, rs.offset_);
1827 LoadRegPlusOffsetToAt(rs);
1833 void Assembler::lw(Register rd, const MemOperand& rs) {
1834 if (is_int16(rs.offset_)) {
1835 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_);
1837 LoadRegPlusOffsetToAt(rs);
1843 void Assembler::lwu(Register rd, const MemOperand& rs) {
1844 if (is_int16(rs.offset_)) {
1845 GenInstrImmediate(LWU, rs.rm(), rd, rs.offset_);
1847 LoadRegPlusOffsetToAt(rs);
1853 void Assembler::lwl(Register rd, const MemOperand& rs) {
1854 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_);
1858 void Assembler::lwr(Register rd, const MemOperand& rs) {
1859 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_);
1863 void Assembler::sb(Register rd, const MemOperand& rs) {
1864 if (is_int16(rs.offset_)) {
1865 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_);
1867 LoadRegPlusOffsetToAt(rs);
1873 void Assembler::sh(Register rd, const MemOperand& rs) {
1874 if (is_int16(rs.offset_)) {
1875 GenInstrImmediate(SH, rs.rm(), rd, rs.offset_);
1877 LoadRegPlusOffsetToAt(rs);
1883 void Assembler::sw(Register rd, const MemOperand& rs) {
1884 if (is_int16(rs.offset_)) {
1885 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_);
1887 LoadRegPlusOffsetToAt(rs);
1893 void Assembler::swl(Register rd, const MemOperand& rs) {
1894 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_);
1898 void Assembler::swr(Register rd, const MemOperand& rs) {
1899 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_);
1909 void Assembler::aui(Register rs, Register rt, int32_t j) {
1911 // 'lui' has zero reg. for rs field.
1913 GenInstrImmediate(LUI, rs, rt, j);
1917 void Assembler::daui(Register rs, Register rt, int32_t j) {
1919 GenInstrImmediate(DAUI, rs, rt, j);
1923 void Assembler::dahi(Register rs, int32_t j) {
1925 GenInstrImmediate(REGIMM, rs, DAHI, j);
1929 void Assembler::dati(Register rs, int32_t j) {
1931 GenInstrImmediate(REGIMM, rs, DATI, j);
1935 void Assembler::ldl(Register rd, const MemOperand& rs) {
1936 GenInstrImmediate(LDL, rs.rm(), rd, rs.offset_);
1940 void Assembler::ldr(Register rd, const MemOperand& rs) {
1941 GenInstrImmediate(LDR, rs.rm(), rd, rs.offset_);
1945 void Assembler::sdl(Register rd, const MemOperand& rs) {
1946 GenInstrImmediate(SDL, rs.rm(), rd, rs.offset_);
1950 void Assembler::sdr(Register rd, const MemOperand& rs) {
1951 GenInstrImmediate(SDR, rs.rm(), rd, rs.offset_);
1955 void Assembler::ld(Register rd, const MemOperand& rs) {
1956 if (is_int16(rs.offset_)) {
1957 GenInstrImmediate(LD, rs.rm(), rd, rs.offset_);
1959 LoadRegPlusOffsetToAt(rs);
1965 void Assembler::sd(Register rd, const MemOperand& rs) {
1966 if (is_int16(rs.offset_)) {
1967 GenInstrImmediate(SD, rs.rm(), rd, rs.offset_);
1969 LoadRegPlusOffsetToAt(rs);
2009 void Assembler::tge(Register rs, Register rt, uint16_t code) {
2011 Instr instr = SPECIAL | TGE | rs.code() << kRsShift
2017 void Assembler::tgeu(Register rs, Register rt, uint16_t code) {
2019 Instr instr = SPECIAL | TGEU | rs.code() << kRsShift
2025 void Assembler::tlt(Register rs, Register rt, uint16_t code) {
2028 SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
2033 void Assembler::tltu(Register rs, Register rt, uint16_t code) {
2036 SPECIAL | TLTU | rs.code() << kRsShift
2042 void Assembler::teq(Register rs, Register rt, uint16_t code) {
2045 SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
2050 void Assembler::tne(Register rs, Register rt, uint16_t code) {
2053 SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
2071 void Assembler::slt(Register rd, Register rs, Register rt) {
2072 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT);
2076 void Assembler::sltu(Register rd, Register rs, Register rt) {
2077 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU);
2081 void Assembler::slti(Register rt, Register rs, int32_t j) {
2082 GenInstrImmediate(SLTI, rs, rt, j);
2086 void Assembler::sltiu(Register rt, Register rs, int32_t j) {
2087 GenInstrImmediate(SLTIU, rs, rt, j);
2092 void Assembler::movz(Register rd, Register rs, Register rt) {
2093 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ);
2097 void Assembler::movn(Register rd, Register rs, Register rt) {
2098 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN);
2102 void Assembler::movt(Register rd, Register rs, uint16_t cc) {
2105 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
2109 void Assembler::movf(Register rd, Register rs, uint16_t cc) {
2112 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
2129 void Assembler::seleqz(Register rs, Register rt, Register rd) {
2131 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELEQZ_S);
2149 void Assembler::selnez(Register rs, Register rt, Register rd) {
2151 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELNEZ_S);
2169 void Assembler::clz(Register rd, Register rs) {
2172 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ);
2174 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 1, CLZ_R6);
2179 void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) {
2183 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS);
2187 void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) {
2191 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT);
2195 void Assembler::pref(int32_t hint, const MemOperand& rs) {
2196 DCHECK(is_uint5(hint) && is_uint16(rs.offset_));
2197 Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift)
2198 | (rs.offset_);
