Lines Matching defs:one
108 Following that, one of the following 3 are allowed (standard
147 simulated one (presumably they communicate via a shared memory
639 * at most one segment-override bit (CS,DS,ES,FS,GS,SS) is set.
3550 better. One problem is, the helper has to calculate both the
4608 the insn is the last one in the basic block, and so emit a jump to
5112 /* Adjust FTOP downwards by one register. */
5119 /* Adjust FTOP downwards by one register when COND is 1:I1. Else
5127 /* Adjust FTOP upwards by one register, and mark the vacated register
5722 /* This is an interesting one. It examines %st(0),
8349 case, but for the memory case, one or the other is OK provided
9078 /* Now convert the op into one with the same arithmetic but that is
10856 One observation is that the steering in the upper and lower 128 bit
13884 /* note, for anyone filling in the mem case: this insn has one
16807 one or both of them and let iropt clean up afterwards (as
16852 one or both of them and let iropt clean up afterwards (as
18214 immediate byte. Is it one we can actually handle? Throw out any
19759 need to emit a side-exit to the insn following this one,
19783 one. */
19807 just one for the mem case and also require LOCK in this case.
19865 /* Check whether F2 or F3 are allowable. For the mem case, one
19935 /* NOTE! this is the one place where a segment override prefix
20353 /* This is the one-and-only place where 64-bit literals are
20603 properly one day) */
20639 address size override, not the operand one. */
21083 (core) only has one IDT and one GDT, just let the guest
21302 one, on the negation of the condition, and continue at
21326 following this one. */
21393 /* All instructions have two operands. One operand is always the
21730 /* Since the e-part is memory only, F2 or F3 (one or the
22058 /* else fall through; maybe one of the decoders below knows what
22883 /* More complex. It's a one-lane-only, hence need to possibly
22884 invert only that one lane. But at least the other lanes are
22896 /* This is the most complex case. One-lane-only, but the args
26228 /* I can't even find any Intel docs for this one. */
27291 IRExpr* one = laneIs32 ? mkU32(1) : mkU64(1);
27297 assign(cond, binop(opEQ, binop(opSHR, lane, shAmt), one));
31307 /* Got a "Special" instruction preamble. Which one is it? */
31605 This implies that any successful decode must use at least one
