Lines Matching refs:X10
70 AA0A014A (orr x10,x10,x10) X3 = client_request ( X4 )
230 #define X10 BITS2(1,0)
1203 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
6200 case 0x10: case 0x12: case 0x14: case 0x16:
7035 imm64 <<= 8; imm64 |= (imm8 & 0x10) ? 0xFF : 0x00;
7330 IRTemp x10 = src;
7333 assign(x11, binop(Iop_InterleaveHI64x2, mkexpr(x10), mkexpr(x10)));
7334 assign(x00, binop(Iop_InterleaveLO64x2, mkexpr(x10), mkexpr(x10)));
7491 case X10:
7540 case X10: amt = 32; break;
7676 case X10:
7889 vassert(size == X01 || size == X10); /* s or h only */
8421 if (size == X11 || (size == X10 && bitQ == 0)) return False;
8465 if (size == X10 && bitQ == 0) return False; // 2s case not allowed
8513 if ((size == X00 || size == X10)
9311 vassert(size >= X00 && size <= X10);
9365 vassert(size == X10 || size == X11);
9403 vassert(size == X10 || size == X11);
9712 if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,0,1,0)) {
9753 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,
9760 if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,1,0,0)) {
9767 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,
9786 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,
9802 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,
9932 if (size >= X10) {
9966 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,
10094 if (size >= X10 && opcode == BITS5(1,1,1,0,1)) {
10103 putQReg128(dd, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(isD ? X11 : X10,
10110 if (bitU == 0 && size >= X10 && opcode == BITS5(1,1,1,1,1)) {
10156 if (bitU == 0 && size >= X10
10191 if (size >= X10 && opcode == BITS4(1,0,0,1)) {
10242 case X10:
10285 case X10:
10720 vassert(size == X10 || size == X11);
10766 vassert(size == X10 || size == X11);
11548 IROp opMXX = (isMIN ? mkVecMINF : mkVecMAXF)(isD ? X11 : X10);
11604 if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,0,1,0)) {
11659 if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,1,0,0)) {
11810 if (bitU == 0 && size <= X10 && opcode == BITS5(0,0,0,0,0)) {
12046 if (size >= X10) {
12087 if (size >= X10 && opcode == BITS5(0,1,1,1,1)) {
12092 IROp op = isFNEG ? (size == X10 ? Iop_Neg32Fx4 : Iop_Neg64Fx2)
12093 : (size == X10 ? Iop_Abs32Fx4 : Iop_Abs64Fx2);
12370 if (size == X10 && opcode == BITS5(1,1,1,0,0)) {
12423 if (size >= X10 && opcode == BITS5(1,1,1,0,1)) {
12440 if (bitU == 1 && size >= X10 && opcode == BITS5(1,1,1,1,1)) {
12487 if (bitU == 0 && size >= X10
12522 if (size >= X10 && opcode == BITS4(1,0,0,1)) {
12565 case X10:
12624 case X10:
12675 case X10:
12720 case X10:
13860 /* orr x10,x10,x10 */) {
