Lines Matching refs:bitS
130 /*--- Helper bits and pieces for deconstructing the ---*/
146 /* Sign extend a N-bit value up to 64 bits, by copying
240 /*--- Helper bits and pieces for creating IR fragments. ---*/
1637 /* Generate IR to get hold of the rounding mode bits in FPCR, and
1642 /* The ARMvfp encoding for rounding mode bits is:
1652 bits 0 and 1.
1653 The rmode bits are at 23:22 in FPSCR.
1658 we don't zero out bits 24 and above, since the assignment to
1714 bits 7:4, and be zero everywhere else.
1719 /* And 'cond' had better produce a value in which only bits 7:4 are
1728 in 4 bits. Hence we are passing a (COND, OP) pair in the lowest
1729 8 bits of the first argument. */
1760 ARM64_CC_OP_ values all fit in 4 bits. Hence we are passing a
1761 (COND, OP) pair in the lowest 8 bits of the first argument. */
1815 /* Build IR to calculate N Z C V in bits 31:28 of the
1989 located in bits 31:28 of the supplied value. */
2095 /* Duplicates the bits at the bottom of the given word to fill the
2097 except for the bottom bits. */
2192 ARM64-encoded (N,Z,C,V) group in the lowest 4 bits of an I64 value.
2206 4 bits of 'nzcv'. */
2218 ix fishes the useful bits out of the IR value, bits 6 and 0, and
2667 /* perform bitfield move on low bits */
2672 /* determine extension bits (sign, zero or dest register) */
2674 /* combine extension bits and result bits */
3092 After extension, the value is shifted left by imm3 bits, which
4175 64 bits -- the caller must ignore that. */
4571 bits of DATAE :: Ity_I64. */
5013 /* Further checks on bits 31:30 and 22 */
5083 /* Further checks on bits 31:30 and 22 */
5161 /* Further checks on bits 31:30 and 22 */
6178 UInt bitS = INSN(12,12);
6192 UInt xx_q_S_sz = (xx << 4) | (bitQ << 3) | (bitS << 2) | sz;
6623 The only part of this we model is FPSR.QC. All other bits
6661 The only parts of NZCV that actually exist are bits 31:28, which
6662 are the N Z C and V bits themselves. Hence the flags thunk provides
6967 /* Expand the VFPExpandImm-style encoding in the bottom 8 bits of
6969 is 64. In the former case, the upper 32 bits of the returned value
6979 /* exp: E bits */
6980 /* frac: F bits */
7075 and SZ bits, typically for vector floating point. */
7144 bottom bits of a V128, with all other bits set to zero. */
7156 lanes of 8 bits. */
7576 This puts the bits we want to inspect at constant offsets
7692 /* Let |new64| be a V128 in which only the lower 64 bits are interesting,
7949 /* Saturation has occurred if any of the shifted-out bits are
7950 nonzero. We get the shifted-out bits by right-shifting the
7969 /* Saturation has occurred if any of the shifted-out bits are
7973 /* qDiff1 is the shifted out bits, and the top bit of the original
7998 /* Saturation has occurred if any of the shifted-out bits are
7999 nonzero. We get the shifted-out bits by right-shifting the
8372 // preL = Vm shifted left 32 bits
8373 // preR = Vn shifted left 32 bits
10064 putQRegLane(dd, 0, mkexpr(res)); /* bits 31-0 or 63-0 */
10066 putQRegLane(dd, 1, mkU32(0)); /* bits 63-32 */
10068 putQRegLane(dd, 1, mkU64(0)); /* bits 127-64 */
10086 putQRegLane(dd, 1, mkU32(0)); /* bits 63-32 */
10088 putQRegLane(dd, 1, mkU64(0)); /* bits 127-64 */
10908 /* Elements now compacted into lower 64 bits */
11307 /* This is a bit tricky. If we're only interested in the lowest 64 bits
12783 The first 3 bits are really "M 0 S", but M and S are always zero.
12858 The first 3 bits are really "M 0 S", but M and S are always zero.
12923 The first 3 bits are really "M 0 S", but M and S are always zero.
12965 The first 3 bits are really "M 0 S", but M and S are always zero.
13159 The first 3 bits are really "M 0 S", but M and S are always zero.
13240 The first 3 bits are really "M 0 S", but M and S are always zero.
13314 The first 3 bits are really "M 0 S", but M and S are always zero.
13352 The first 3 bits are really "sf 0 S", but S is always zero.
13472 The first 3 bits are really "sf 0 S", but S is always zero.
13807 // A macro to fish bits out of 'insn'.
