Lines Matching defs:pc
12584 responsible for all validation of parameters. For LDMxx, if PC is
12724 register and PC in the register list is a return for purposes of branch
12745 // write the PC, just use the low level put:
14885 /* According to the Cortex A8 TRM Sec. 5.2.1, MOV PC, r14 is a
15187 base register and PC as the destination register is a return for
17373 a write to the guest PC. As usual we rely on ir_opt to tidy
17606 UInt pc = guest_R15_curr_instr_notENC;
17607 vassert(0 == (pc & 1));
17609 UInt pageoff = pc & 0xFFF;
17615 UShort* hwp = (UShort*)(HWord)pc;
17622 == ( pc & 0xFFFFF000 ) );
18547 /* Now the transfers, not including PC */
18574 that the new PC value is encoded exactly as we need it to
18584 DIP("pop {%s0x%04x}\n", bitR ? "pc," : "", regList & 0xFF);
18773 /* ---------------- ADD rD, PC, #imm8 * 4 ---------------- */
18775 /* rD = align4(PC) + imm8 * 4 */
18782 DIP("add r%u, pc, #%u\n", rD, imm8 * 4);
18828 /* ------------- LDR Rd, [PC, #imm8 * 4] ------------- */
18829 /* LDR Rd, [align4(PC) + imm8 * 4] */
18843 DIP("ldr r%u, [pc, #%u]\n", rD, imm8 * 4);
19292 // We'll be writing the PC. Hence:
19329 /* but allow "add.w reg, sp, #constT" for reg != PC */
19356 /* but allow "addw reg, sp, #uimm12" for reg != PC */
20172 /* We'll do the write to the PC just below */
20341 /* We'll do the write to the PC just below */
20407 // only pc supports #-imm12
20494 /* We'll do the write to the PC just below */
20540 /* It's OK to use PC as the base register only in the
20541 following case: ldrd Rt, Rt2, [PC, #+/-imm8] */
20964 /* rD = align4(PC) + imm32 */
20973 DIP("add r%u, pc, #%u\n", rD, imm32);
21096 /* rD = align4(PC) - imm32 */
21105 DIP("sub r%u, pc, #%u\n", rD, imm32);
21815 /* -------------- (T3) PLI PC+/-#imm12 -------------- */
21817 pli [PC, #+/-imm12]
21824 DIP("pli [pc, #%c%u]\n", bU == 1 ? '+' : '-', imm12);
