Lines Matching refs:lane
513 least significant lane (rightmost in the register). */
7056 /* Lowest 32-bit lane only SSE binary operation, G = G `op` E. */
7091 /* Lower 64-bit lane only SSE binary operation, G = G `op` E. */
7165 /* Lowest 32-bit lane only unary SSE operation, G = op(E). */
7208 /* Lowest 64-bit lane only unary SSE operation, G = op(E). */
7788 values (aa,bb), computes, for each lane:
7827 value aa, computes, for each lane
8531 assign( argR, getXMMRegLane32F( eregOfRM(modrm), 0/*lowest lane*/ ) );
8542 assign( argL, getXMMRegLane32F( gregOfRM(modrm), 0/*lowest lane*/ ) );
8874 put it into the specified lane of mmx(G). */
8877 mmx reg. t4 is the new lane value. t5 is the original
8879 Int lane;
8892 lane = insn[3+1-1];
8893 DIP("pinsrw $%d,%s,%s\n", (Int)lane,
8899 lane = insn[3+alen-1];
8901 DIP("pinsrw $%d,%s,%s\n", (Int)lane,
8906 switch (lane & 3) {
9172 putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/,
9179 putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/,
9195 1/*upper lane*/ ) );
9210 0/*lower lane*/,
9217 putXMMRegLane64( gregOfRM(modrm), 0/*lower lane*/,
9233 0/*lower lane*/ ) );
9596 assign( argR, getXMMRegLane64F( eregOfRM(modrm), 0/*lowest lane*/ ) );
9607 assign( argL, getXMMRegLane64F( gregOfRM(modrm), 0/*lowest lane*/ ) );
10382 putXMMRegLane64( gregOfRM(modrm), 1/*upper lane*/,
10399 1/*upper lane*/ ) );
10416 putXMMRegLane64( gregOfRM(modrm), 0/*lower lane*/,
10433 0/*lower lane*/ ) );
10967 put it into the specified lane of xmm(G). */
10969 Int lane;
10976 lane = insn[3+1-1];
10977 DIP("pinsrw $%d,%s,%s\n", (Int)lane,
10983 lane = insn[3+alen-1];
10985 DIP("pinsrw $%d,%s,%s\n", (Int)lane,
10990 putXMMRegLane16( gregOfRM(modrm), lane & 7, mkexpr(t4) );
