Lines Matching refs:Ain
592 i->Ain.Imm64.imm64 = imm64;
593 i->Ain.Imm64.dst = dst;
599 i->Ain.Alu64R.op = op;
600 i->Ain.Alu64R.src = src;
601 i->Ain.Alu64R.dst = dst;
607 i->Ain.Alu64M.op = op;
608 i->Ain.Alu64M.src = src;
609 i->Ain.Alu64M.dst = dst;
616 i->Ain.Sh64.op = op;
617 i->Ain.Sh64.src = src;
618 i->Ain.Sh64.dst = dst;
624 i->Ain.Test64.imm32 = imm32;
625 i->Ain.Test64.dst = dst;
631 i->Ain.Unary64.op = op;
632 i->Ain.Unary64.dst = dst;
638 i->Ain.Lea64.am = am;
639 i->Ain.Lea64.dst = dst;
645 i->Ain.Alu32R.op = op;
646 i->Ain.Alu32R.src = src;
647 i->Ain.Alu32R.dst = dst;
658 i->Ain.MulL.syned = syned;
659 i->Ain.MulL.src = src;
665 i->Ain.Div.syned = syned;
666 i->Ain.Div.sz = sz;
667 i->Ain.Div.src = src;
674 i->Ain.Push.src = src;
681 i->Ain.Call.cond = cond;
682 i->Ain.Call.target = target;
683 i->Ain.Call.regparms = regparms;
684 i->Ain.Call.rloc = rloc;
694 i->Ain.XDirect.dstGA = dstGA;
695 i->Ain.XDirect.amRIP = amRIP;
696 i->Ain.XDirect.cond = cond;
697 i->Ain.XDirect.toFastEP = toFastEP;
704 i->Ain.XIndir.dstGA = dstGA;
705 i->Ain.XIndir.amRIP = amRIP;
706 i->Ain.XIndir.cond = cond;
713 i->Ain.XAssisted.dstGA = dstGA;
714 i->Ain.XAssisted.amRIP = amRIP;
715 i->Ain.XAssisted.cond = cond;
716 i->Ain.XAssisted.jk = jk;
723 i->Ain.CMov64.cond = cond;
724 i->Ain.CMov64.src = src;
725 i->Ain.CMov64.dst = dst;
733 i->Ain.CLoad.cond = cond;
734 i->Ain.CLoad.szB = szB;
735 i->Ain.CLoad.addr = addr;
736 i->Ain.CLoad.dst = dst;
744 i->Ain.CStore.cond = cond;
745 i->Ain.CStore.szB = szB;
746 i->Ain.CStore.src = src;
747 i->Ain.CStore.addr = addr;
754 i->Ain.MovxLQ.syned = syned;
755 i->Ain.MovxLQ.src = src;
756 i->Ain.MovxLQ.dst = dst;
763 i->Ain.LoadEX.szSmall = szSmall;
764 i->Ain.LoadEX.syned = syned;
765 i->Ain.LoadEX.src = src;
766 i->Ain.LoadEX.dst = dst;
773 i->Ain.Store.sz = sz;
774 i->Ain.Store.src = src;
775 i->Ain.Store.dst = dst;
782 i->Ain.Set64.cond = cond;
783 i->Ain.Set64.dst = dst;
789 i->Ain.Bsfr64.isFwds = isFwds;
790 i->Ain.Bsfr64.src = src;
791 i->Ain.Bsfr64.dst = dst;
802 i->Ain.ACAS.addr = addr;
803 i->Ain.ACAS.sz = sz;
810 i->Ain.DACAS.addr = addr;
811 i->Ain.DACAS.sz = sz;
820 i->Ain.A87Free.nregs = nregs;
828 i->Ain.A87PushPop.addr = addr;
829 i->Ain.A87PushPop.isPush = isPush;
830 i->Ain.A87PushPop.szB = szB;
838 i->Ain.A87FpOp.op = op;
845 i->Ain.A87LdCW.addr = addr;
852 i->Ain.A87StSW.addr = addr;
858 i->Ain.LdMXCSR.addr = addr;
864 i->Ain.SseUComIS.sz = toUChar(sz);
865 i->Ain.SseUComIS.srcL = srcL;
866 i->Ain.SseUComIS.srcR = srcR;
867 i->Ain.SseUComIS.dst = dst;
874 i->Ain.SseSI2SF.szS = toUChar(szS);
875 i->Ain.SseSI2SF.szD = toUChar(szD);
876 i->Ain.SseSI2SF.src = src;
877 i->Ain.SseSI2SF.dst = dst;
885 i->Ain.SseSF2SI.szS = toUChar(szS);
886 i->Ain.SseSF2SI.szD = toUChar(szD);
887 i->Ain.SseSF2SI.src = src;
888 i->Ain.SseSF2SI.dst = dst;
897 i->Ain.SseSDSS.from64 = from64;
898 i->Ain.SseSDSS.src = src;
899 i->Ain.SseSDSS.dst = dst;
906 i->Ain.SseLdSt.isLoad = isLoad;
907 i->Ain.SseLdSt.sz = toUChar(sz);
908 i->Ain.SseLdSt.reg = reg;
909 i->Ain.SseLdSt.addr = addr;
917 i->Ain.SseLdzLO.sz = sz;
918 i->Ain.SseLdzLO.reg = reg;
919 i->Ain.SseLdzLO.addr = addr;
926 i->Ain.Sse32Fx4.op = op;
927 i->Ain.Sse32Fx4.src = src;
928 i->Ain.Sse32Fx4.dst = dst;
935 i->Ain.Sse32FLo.op = op;
936 i->Ain.Sse32FLo.src = src;
937 i->Ain.Sse32FLo.dst = dst;
944 i->Ain.Sse64Fx2.op = op;
945 i->Ain.Sse64Fx2.src = src;
946 i->Ain.Sse64Fx2.dst = dst;
953 i->Ain.Sse64FLo.op = op;
954 i->Ain.Sse64FLo.src = src;
955 i->Ain.Sse64FLo.dst = dst;
962 i->Ain.SseReRg.op = op;
963 i->Ain.SseReRg.src = re;
964 i->Ain.SseReRg.dst = rg;
970 i->Ain.SseCMov.cond = cond;
971 i->Ain.SseCMov.src = src;
972 i->Ain.SseCMov.dst = dst;
979 i->Ain.SseShuf.order = order;
980 i->Ain.SseShuf.src = src;
981 i->Ain.SseShuf.dst = dst;
989 //uu i->Ain.AvxLdSt.isLoad = isLoad;
990 //uu i->Ain.AvxLdSt.reg = reg;
991 //uu i->Ain.AvxLdSt.addr = addr;
997 //uu i->Ain.AvxReRg.op = op;
998 //uu i->Ain.AvxReRg.src = re;
999 //uu i->Ain.AvxReRg.dst = rg;
1006 i->Ain.EvCheck.amCounter = amCounter;
1007 i->Ain.EvCheck.amFailAddr = amFailAddr;
1021 vex_printf("movabsq $0x%llx,", i->Ain.Imm64.imm64);
1022 ppHRegAMD64(i->Ain.Imm64.dst);
1025 vex_printf("%sq ", showAMD64AluOp(i->Ain.Alu64R.op));
1026 ppAMD64RMI(i->Ain.Alu64R.src);
1028 ppHRegAMD64(i->Ain.Alu64R.dst);
1031 vex_printf("%sq ", showAMD64AluOp(i->Ain.Alu64M.op));
1032 ppAMD64RI(i->Ain.Alu64M.src);
1034 ppAMD64AMode(i->Ain.Alu64M.dst);
1037 vex_printf("%sq ", showAMD64ShiftOp(i->Ain.Sh64.op));
1038 if (i->Ain.Sh64.src == 0)
1041 vex_printf("$%d,", (Int)i->Ain.Sh64.src);
1042 ppHRegAMD64(i->Ain.Sh64.dst);
1045 vex_printf("testq $%d,", (Int)i->Ain.Test64.imm32);
1046 ppHRegAMD64(i->Ain.Test64.dst);
1049 vex_printf("%sq ", showAMD64UnaryOp(i->Ain.Unary64.op));
1050 ppHRegAMD64(i->Ain.Unary64.dst);
1054 ppAMD64AMode(i->Ain.Lea64.am);
1056 ppHRegAMD64(i->Ain.Lea64.dst);
1059 vex_printf("%sl ", showAMD64AluOp(i->Ain.Alu32R.op));
1060 ppAMD64RMI_lo32(i->Ain.Alu32R.src);
1062 ppHRegAMD64_lo32(i->Ain.Alu32R.dst);
1065 vex_printf("%cmulq ", i->Ain.MulL.syned ? 's' : 'u');
1066 ppAMD64RM(i->Ain.MulL.src);
1070 i->Ain.Div.syned ? 's' : 'u',
1071 showAMD64ScalarSz(i->Ain.Div.sz));
1072 ppAMD64RM(i->Ain.Div.src);
1076 ppAMD64RMI(i->Ain.Push.src);
1080 i->Ain.Call.cond==Acc_ALWAYS
1081 ? "" : showAMD64CondCode(i->Ain.Call.cond),
1082 i->Ain.Call.regparms );
1083 ppRetLoc(i->Ain.Call.rloc);
1084 vex_printf("] 0x%llx", i->Ain.Call.target);
1090 showAMD64CondCode(i->Ain.XDirect.cond));
1091 vex_printf("movabsq $0x%llx,%%r11; ", i->Ain.XDirect.dstGA);
1093 ppAMD64AMode(i->Ain.XDirect.amRIP);
1096 i->Ain.XDirect.toFastEP ? "fast" : "slow");
1101 showAMD64CondCode(i->Ain.XIndir.cond));
1103 ppHRegAMD64(i->Ain.XIndir.dstGA);
1105 ppAMD64AMode(i->Ain.XIndir.amRIP);
1111 showAMD64CondCode(i->Ain.XAssisted.cond));
1113 ppHRegAMD64(i->Ain.XAssisted.dstGA);
1115 ppAMD64AMode(i->Ain.XAssisted.amRIP);
1117 (Int)i->Ain.XAssisted.jk);
1122 vex_printf("cmov%s ", showAMD64CondCode(i->Ain.CMov64.cond));
1123 ppHRegAMD64(i->Ain.CMov64.src);
1125 ppHRegAMD64(i->Ain.CMov64.dst);
1129 showAMD64CondCode(i->Ain.CLoad.cond));
1130 vex_printf("mov%c ", i->Ain.CLoad.szB == 4 ? 'l' : 'q');
1131 ppAMD64AMode(i->Ain.CLoad.addr);
1133 (i->Ain.CLoad.szB == 4 ? ppHRegAMD64_lo32 : ppHRegAMD64)
1134 (i->Ain.CLoad.dst);
1139 showAMD64CondCode(i->Ain.CStore.cond));
1140 vex_printf("mov%c ", i->Ain.CStore.szB == 4 ? 'l' : 'q');
1141 (i->Ain.CStore.szB == 4 ? ppHRegAMD64_lo32 : ppHRegAMD64)
1142 (i->Ain.CStore.src);
1144 ppAMD64AMode(i->Ain.CStore.addr);
1149 vex_printf("mov%clq ", i->Ain.MovxLQ.syned ? 's' : 'z');
1150 ppHRegAMD64_lo32(i->Ain.MovxLQ.src);
1152 ppHRegAMD64(i->Ain.MovxLQ.dst);
1155 if (i->Ain.LoadEX.szSmall==4 && !i->Ain.LoadEX.syned) {
1157 ppAMD64AMode(i->Ain.LoadEX.src);
1159 ppHRegAMD64_lo32(i->Ain.LoadEX.dst);
1162 i->Ain.LoadEX.syned ? 's' : 'z',
1163 i->Ain.LoadEX.szSmall==1
1165 : (i->Ain.LoadEX.szSmall==2 ? 'w' : 'l'));
1166 ppAMD64AMode(i->Ain.LoadEX.src);
1168 ppHRegAMD64(i->Ain.LoadEX.dst);
1172 vex_printf("mov%c ", i->Ain.Store.sz==1 ? 'b'
1173 : (i->Ain.Store.sz==2 ? 'w' : 'l'));
1174 ppHRegAMD64(i->Ain.Store.src);
1176 ppAMD64AMode(i->Ain.Store.dst);
1179 vex_printf("setq%s ", showAMD64CondCode(i->Ain.Set64.cond));
1180 ppHRegAMD64(i->Ain.Set64.dst);
1183 vex_printf("bs%cq ", i->Ain.Bsfr64.isFwds ? 'f' : 'r');
1184 ppHRegAMD64(i->Ain.Bsfr64.src);
1186 ppHRegAMD64(i->Ain.Bsfr64.dst);
1193 i->Ain.ACAS.sz==1 ? 'b' : i->Ain.ACAS.sz==2 ? 'w'
1194 : i->Ain.ACAS.sz==4 ? 'l' : 'q' );
1196 ppAMD64AMode(i->Ain.ACAS.addr);
1200 (Int)(2 * i->Ain.DACAS.sz));
1201 ppAMD64AMode(i->Ain.DACAS.addr);
1204 vex_printf("ffree %%st(7..%d)", 8 - i->Ain.A87Free.nregs );
1207 vex_printf(i->Ain.A87PushPop.isPush ? "fld%c " : "fstp%c ",
1208 i->Ain.A87PushPop.szB == 4 ? 's' : 'l');
1209 ppAMD64AMode(i->Ain.A87PushPop.addr);
1212 vex_printf("f%s", showA87FpOp(i->Ain.A87FpOp.op));
1216 ppAMD64AMode(i->Ain.A87LdCW.addr);
1220 ppAMD64AMode(i->Ain.A87StSW.addr);
1224 ppAMD64AMode(i->Ain.LdMXCSR.addr);
1227 vex_printf("ucomis%s ", i->Ain.SseUComIS.sz==4 ? "s" : "d");
1228 ppHRegAMD64(i->Ain.SseUComIS.srcL);
1230 ppHRegAMD64(i->Ain.SseUComIS.srcR);
1232 ppHRegAMD64(i->Ain.SseUComIS.dst);
1235 vex_printf("cvtsi2s%s ", i->Ain.SseSI2SF.szD==4 ? "s" : "d");
1236 (i->Ain.SseSI2SF.szS==4 ? ppHRegAMD64_lo32 : ppHRegAMD64)
1237 (i->Ain.SseSI2SF.src);
1239 ppHRegAMD64(i->Ain.SseSI2SF.dst);
1242 vex_printf("cvts%s2si ", i->Ain.SseSF2SI.szS==4 ? "s" : "d");
1243 ppHRegAMD64(i->Ain.SseSF2SI.src);
1245 (i->Ain.SseSF2SI.szD==4 ? ppHRegAMD64_lo32 : ppHRegAMD64)
1246 (i->Ain.SseSF2SI.dst);
1249 vex_printf(i->Ain.SseSDSS.from64 ? "cvtsd2ss " : "cvtss2sd ");
1250 ppHRegAMD64(i->Ain.SseSDSS.src);
1252 ppHRegAMD64(i->Ain.SseSDSS.dst);
1255 switch (i->Ain.SseLdSt.sz) {
1261 if (i->Ain.SseLdSt.isLoad) {
1262 ppAMD64AMode(i->Ain.SseLdSt.addr);
1264 ppHRegAMD64(i->Ain.SseLdSt.reg);
1266 ppHRegAMD64(i->Ain.SseLdSt.reg);
1268 ppAMD64AMode(i->Ain.SseLdSt.addr);
1272 vex_printf("movs%s ", i->Ain.SseLdzLO.sz==4 ? "s" : "d");
1273 ppAMD64AMode(i->Ain.SseLdzLO.addr);
1275 ppHRegAMD64(i->Ain.SseLdzLO.reg);
1278 vex_printf("%sps ", showAMD64SseOp(i->Ain.Sse32Fx4.op));
1279 ppHRegAMD64(i->Ain.Sse32Fx4.src);
1281 ppHRegAMD64(i->Ain.Sse32Fx4.dst);
1284 vex_printf("%sss ", showAMD64SseOp(i->Ain.Sse32FLo.op));
1285 ppHRegAMD64(i->Ain.Sse32FLo.src);
1287 ppHRegAMD64(i->Ain.Sse32FLo.dst);
1290 vex_printf("%spd ", showAMD64SseOp(i->Ain.Sse64Fx2.op));
1291 ppHRegAMD64(i->Ain.Sse64Fx2.src);
1293 ppHRegAMD64(i->Ain.Sse64Fx2.dst);
1296 vex_printf("%ssd ", showAMD64SseOp(i->Ain.Sse64FLo.op));
1297 ppHRegAMD64(i->Ain.Sse64FLo.src);
1299 ppHRegAMD64(i->Ain.Sse64FLo.dst);
1302 vex_printf("%s ", showAMD64SseOp(i->Ain.SseReRg.op));
1303 ppHRegAMD64(i->Ain.SseReRg.src);
1305 ppHRegAMD64(i->Ain.SseReRg.dst);
1308 vex_printf("cmov%s ", showAMD64CondCode(i->Ain.SseCMov.cond));
1309 ppHRegAMD64(i->Ain.SseCMov.src);
1311 ppHRegAMD64(i->Ain.SseCMov.dst);
1314 vex_printf("pshufd $0x%x,", i->Ain.SseShuf.order);
1315 ppHRegAMD64(i->Ain.SseShuf.src);
1317 ppHRegAMD64(i->Ain.SseShuf.dst);
1321 //uu if (i->Ain.AvxLdSt.isLoad) {
1322 //uu ppAMD64AMode(i->Ain.AvxLdSt.addr);
1324 //uu ppHRegAMD64(i->Ain.AvxLdSt.reg);
1326 //uu ppHRegAMD64(i->Ain.AvxLdSt.reg);
1328 //uu ppAMD64AMode(i->Ain.AvxLdSt.addr);
1332 //uu vex_printf("v%s ", showAMD64SseOp(i->Ain.SseReRg.op));
1333 //uu ppHRegAMD64(i->Ain.AvxReRg.src);
1335 //uu ppHRegAMD64(i->Ain.AvxReRg.dst);
1339 ppAMD64AMode(i->Ain.EvCheck.amCounter);
1341 ppAMD64AMode(i->Ain.EvCheck.amFailAddr);
1361 addHRegUse(u, HRmWrite, i->Ain.Imm64.dst);
1364 addRegUsage_AMD64RMI(u, i->Ain.Alu64R.src);
1365 if (i->Ain.Alu64R.op == Aalu_MOV) {
1366 addHRegUse(u, HRmWrite, i->Ain.Alu64R.dst);
1369 if (i->Ain.Alu64R.op == Aalu_CMP) {
1370 addHRegUse(u, HRmRead, i->Ain.Alu64R.dst);
1373 addHRegUse(u, HRmModify, i->Ain.Alu64R.dst);
1376 addRegUsage_AMD64RI(u, i->Ain.Alu64M.src);
1377 addRegUsage_AMD64AMode(u, i->Ain.Alu64M.dst);
1380 addHRegUse(u, HRmModify, i->Ain.Sh64.dst);
1381 if (i->Ain.Sh64.src == 0)
1385 addHRegUse(u, HRmRead, i->Ain.Test64.dst);
1388 addHRegUse(u, HRmModify, i->Ain.Unary64.dst);
1391 addRegUsage_AMD64AMode(u, i->Ain.Lea64.am);
1392 addHRegUse(u, HRmWrite, i->Ain.Lea64.dst);
1395 vassert(i->Ain.Alu32R.op != Aalu_MOV);
1396 addRegUsage_AMD64RMI(u, i->Ain.Alu32R.src);
1397 if (i->Ain.Alu32R.op == Aalu_CMP) {
1398 addHRegUse(u, HRmRead, i->Ain.Alu32R.dst);
1401 addHRegUse(u, HRmModify, i->Ain.Alu32R.dst);
1404 addRegUsage_AMD64RM(u, i->Ain.MulL.src, HRmRead);
1409 addRegUsage_AMD64RM(u, i->Ain.Div.src, HRmRead);
1414 addRegUsage_AMD64RMI(u, i->Ain.Push.src);
1448 switch (i->Ain.Call.regparms) {
1474 addRegUsage_AMD64AMode(u, i->Ain.XDirect.amRIP);
1478 addHRegUse(u, HRmRead, i->Ain.XIndir.dstGA);
1479 addRegUsage_AMD64AMode(u, i->Ain.XIndir.amRIP);
1483 addHRegUse(u, HRmRead, i->Ain.XAssisted.dstGA);
1484 addRegUsage_AMD64AMode(u, i->Ain.XAssisted.amRIP);
1487 addHRegUse(u, HRmRead, i->Ain.CMov64.src);
1488 addHRegUse(u, HRmModify, i->Ain.CMov64.dst);
1491 addRegUsage_AMD64AMode(u, i->Ain.CLoad.addr);
1492 addHRegUse(u, HRmModify, i->Ain.CLoad.dst);
1495 addRegUsage_AMD64AMode(u, i->Ain.CStore.addr);
1496 addHRegUse(u, HRmRead, i->Ain.CStore.src);
1499 addHRegUse(u, HRmRead, i->Ain.MovxLQ.src);
1500 addHRegUse(u, HRmWrite, i->Ain.MovxLQ.dst);
1503 addRegUsage_AMD64AMode(u, i->Ain.LoadEX.src);
1504 addHRegUse(u, HRmWrite, i->Ain.LoadEX.dst);
1507 addHRegUse(u, HRmRead, i->Ain.Store.src);
1508 addRegUsage_AMD64AMode(u, i->Ain.Store.dst);
1511 addHRegUse(u, HRmWrite, i->Ain.Set64.dst);
1514 addHRegUse(u, HRmRead, i->Ain.Bsfr64.src);
1515 addHRegUse(u, HRmWrite, i->Ain.Bsfr64.dst);
1520 addRegUsage_AMD64AMode(u, i->Ain.ACAS.addr);
1525 addRegUsage_AMD64AMode(u, i->Ain.DACAS.addr);
1534 addRegUsage_AMD64AMode(u, i->Ain.A87PushPop.addr);
1539 addRegUsage_AMD64AMode(u, i->Ain.A87LdCW.addr);
1542 addRegUsage_AMD64AMode(u, i->Ain.A87StSW.addr);
1545 addRegUsage_AMD64AMode(u, i->Ain.LdMXCSR.addr);
1548 addHRegUse(u, HRmRead, i->Ain.SseUComIS.srcL);
1549 addHRegUse(u, HRmRead, i->Ain.SseUComIS.srcR);
1550 addHRegUse(u, HRmWrite, i->Ain.SseUComIS.dst);
1553 addHRegUse(u, HRmRead, i->Ain.SseSI2SF.src);
1554 addHRegUse(u, HRmWrite, i->Ain.SseSI2SF.dst);
1557 addHRegUse(u, HRmRead, i->Ain.SseSF2SI.src);
1558 addHRegUse(u, HRmWrite, i->Ain.SseSF2SI.dst);
1561 addHRegUse(u, HRmRead, i->Ain.SseSDSS.src);
1562 addHRegUse(u, HRmWrite, i->Ain.SseSDSS.dst);
1565 addRegUsage_AMD64AMode(u, i->Ain.SseLdSt.addr);
1566 addHRegUse(u, i->Ain.SseLdSt.isLoad ? HRmWrite : HRmRead,
1567 i->Ain.SseLdSt.reg);
1570 addRegUsage_AMD64AMode(u, i->Ain.SseLdzLO.addr);
1571 addHRegUse(u, HRmWrite, i->Ain.SseLdzLO.reg);
1574 vassert(i->Ain.Sse32Fx4.op != Asse_MOV);
1575 unary = toBool( i->Ain.Sse32Fx4.op == Asse_RCPF
1576 || i->Ain.Sse32Fx4.op == Asse_RSQRTF
1577 || i->Ain.Sse32Fx4.op == Asse_SQRTF );
1578 addHRegUse(u, HRmRead, i->Ain.Sse32Fx4.src);
1580 i->Ain.Sse32Fx4.dst);
1583 vassert(i->Ain.Sse32FLo.op != Asse_MOV);
1584 unary = toBool( i->Ain.Sse32FLo.op == Asse_RCPF
1585 || i->Ain.Sse32FLo.op == Asse_RSQRTF
1586 || i->Ain.Sse32FLo.op == Asse_SQRTF );
1587 addHRegUse(u, HRmRead, i->Ain.Sse32FLo.src);
1589 i->Ain.Sse32FLo.dst);
1592 vassert(i->Ain.Sse64Fx2.op != Asse_MOV);
1593 unary = toBool( i->Ain.Sse64Fx2.op == Asse_RCPF
1594 || i->Ain.Sse64Fx2.op == Asse_RSQRTF
1595 || i->Ain.Sse64Fx2.op == Asse_SQRTF );
1596 addHRegUse(u, HRmRead, i->Ain.Sse64Fx2.src);
1598 i->Ain.Sse64Fx2.dst);
1601 vassert(i->Ain.Sse64FLo.op != Asse_MOV);
1602 unary = toBool( i->Ain.Sse64FLo.op == Asse_RCPF
1603 || i->Ain.Sse64FLo.op == Asse_RSQRTF
1604 || i->Ain.Sse64FLo.op == Asse_SQRTF );
1605 addHRegUse(u, HRmRead, i->Ain.Sse64FLo.src);
1607 i->Ain.Sse64FLo.dst);
1610 if ( (i->Ain.SseReRg.op == Asse_XOR
1611 || i->Ain.SseReRg.op == Asse_CMPEQ32)
1612 && sameHReg(i->Ain.SseReRg.src, i->Ain.SseReRg.dst)) {
1617 addHRegUse(u, HRmWrite, i->Ain.SseReRg.dst);
1619 addHRegUse(u, HRmRead, i->Ain.SseReRg.src);
1620 addHRegUse(u, i->Ain.SseReRg.op == Asse_MOV
1622 i->Ain.SseReRg.dst);
1626 addHRegUse(u, HRmRead, i->Ain.SseCMov.src);
1627 addHRegUse(u, HRmModify, i->Ain.SseCMov.dst);
1630 addHRegUse(u, HRmRead, i->Ain.SseShuf.src);
1631 addHRegUse(u, HRmWrite, i->Ain.SseShuf.dst);
1634 //uu addRegUsage_AMD64AMode(u, i->Ain.AvxLdSt.addr);
1635 //uu addHRegUse(u, i->Ain.AvxLdSt.isLoad ? HRmWrite : HRmRead,
1636 //uu i->Ain.AvxLdSt.reg);
1639 //uu if ( (i->Ain.AvxReRg.op == Asse_XOR
1640 //uu || i->Ain.AvxReRg.op == Asse_CMPEQ32)
1641 //uu && i->Ain.AvxReRg.src == i->Ain.AvxReRg.dst) {
1643 //uu addHRegUse(u, HRmWrite, i->Ain.AvxReRg.dst);
1645 //uu addHRegUse(u, HRmRead, i->Ain.AvxReRg.src);
1646 //uu addHRegUse(u, i->Ain.AvxReRg.op == Asse_MOV
1648 //uu i->Ain.AvxReRg.dst);
1654 addRegUsage_AMD64AMode(u, i->Ain.EvCheck.amCounter);
1655 addRegUsage_AMD64AMode(u, i->Ain.EvCheck.amFailAddr);
1677 mapReg(m, &i->Ain.Imm64.dst);
1680 mapRegs_AMD64RMI(m, i->Ain.Alu64R.src);
1681 mapReg(m, &i->Ain.Alu64R.dst);
1684 mapRegs_AMD64RI(m, i->Ain.Alu64M.src);
1685 mapRegs_AMD64AMode(m, i->Ain.Alu64M.dst);
1688 mapReg(m, &i->Ain.Sh64.dst);
1691 mapReg(m, &i->Ain.Test64.dst);
1694 mapReg(m, &i->Ain.Unary64.dst);
1697 mapRegs_AMD64AMode(m, i->Ain.Lea64.am);
1698 mapReg(m, &i->Ain.Lea64.dst);
1701 mapRegs_AMD64RMI(m, i->Ain.Alu32R.src);
1702 mapReg(m, &i->Ain.Alu32R.dst);
1705 mapRegs_AMD64RM(m, i->Ain.MulL.src);
1708 mapRegs_AMD64RM(m, i->Ain.Div.src);
1711 mapRegs_AMD64RMI(m, i->Ain.Push.src);
1716 mapRegs_AMD64AMode(m, i->Ain.XDirect.amRIP);
1719 mapReg(m, &i->Ain.XIndir.dstGA);
1720 mapRegs_AMD64AMode(m, i->Ain.XIndir.amRIP);
1723 mapReg(m, &i->Ain.XAssisted.dstGA);
1724 mapRegs_AMD64AMode(m, i->Ain.XAssisted.amRIP);
1727 mapReg(m, &i->Ain.CMov64.src);
1728 mapReg(m, &i->Ain.CMov64.dst);
1731 mapRegs_AMD64AMode(m, i->Ain.CLoad.addr);
1732 mapReg(m, &i->Ain.CLoad.dst);
1735 mapRegs_AMD64AMode(m, i->Ain.CStore.addr);
1736 mapReg(m, &i->Ain.CStore.src);
1739 mapReg(m, &i->Ain.MovxLQ.src);
1740 mapReg(m, &i->Ain.MovxLQ.dst);
1743 mapRegs_AMD64AMode(m, i->Ain.LoadEX.src);
1744 mapReg(m, &i->Ain.LoadEX.dst);
1747 mapReg(m, &i->Ain.Store.src);
1748 mapRegs_AMD64AMode(m, i->Ain.Store.dst);
1751 mapReg(m, &i->Ain.Set64.dst);
1754 mapReg(m, &i->Ain.Bsfr64.src);
1755 mapReg(m, &i->Ain.Bsfr64.dst);
1760 mapRegs_AMD64AMode(m, i->Ain.ACAS.addr);
1763 mapRegs_AMD64AMode(m, i->Ain.DACAS.addr);
1768 mapRegs_AMD64AMode(m, i->Ain.A87PushPop.addr);
1773 mapRegs_AMD64AMode(m, i->Ain.A87LdCW.addr);
1776 mapRegs_AMD64AMode(m, i->Ain.A87StSW.addr);
1779 mapRegs_AMD64AMode(m, i->Ain.LdMXCSR.addr);
1782 mapReg(m, &i->Ain.SseUComIS.srcL);
1783 mapReg(m, &i->Ain.SseUComIS.srcR);
1784 mapReg(m, &i->Ain.SseUComIS.dst);
1787 mapReg(m, &i->Ain.SseSI2SF.src);
1788 mapReg(m, &i->Ain.SseSI2SF.dst);
1791 mapReg(m, &i->Ain.SseSF2SI.src);
1792 mapReg(m, &i->Ain.SseSF2SI.dst);
1795 mapReg(m, &i->Ain.SseSDSS.src);
1796 mapReg(m, &i->Ain.SseSDSS.dst);
1799 mapReg(m, &i->Ain.SseLdSt.reg);
1800 mapRegs_AMD64AMode(m, i->Ain.SseLdSt.addr);
1803 mapReg(m, &i->Ain.SseLdzLO.reg);
1804 mapRegs_AMD64AMode(m, i->Ain.SseLdzLO.addr);
1807 mapReg(m, &i->Ain.Sse32Fx4.src);
1808 mapReg(m, &i->Ain.Sse32Fx4.dst);
1811 mapReg(m, &i->Ain.Sse32FLo.src);
1812 mapReg(m, &i->Ain.Sse32FLo.dst);
1815 mapReg(m, &i->Ain.Sse64Fx2.src);
1816 mapReg(m, &i->Ain.Sse64Fx2.dst);
1819 mapReg(m, &i->Ain.Sse64FLo.src);
1820 mapReg(m, &i->Ain.Sse64FLo.dst);
1823 mapReg(m, &i->Ain.SseReRg.src);
1824 mapReg(m, &i->Ain.SseReRg.dst);
1827 mapReg(m, &i->Ain.SseCMov.src);
1828 mapReg(m, &i->Ain.SseCMov.dst);
1831 mapReg(m, &i->Ain.SseShuf.src);
1832 mapReg(m, &i->Ain.SseShuf.dst);
1835 //uu mapReg(m, &i->Ain.AvxLdSt.reg);
1836 //uu mapRegs_AMD64AMode(m, i->Ain.AvxLdSt.addr);
1839 //uu mapReg(m, &i->Ain.AvxReRg.src);
1840 //uu mapReg(m, &i->Ain.AvxReRg.dst);
1845 mapRegs_AMD64AMode(m, i->Ain.EvCheck.amCounter);
1846 mapRegs_AMD64AMode(m, i->Ain.EvCheck.amFailAddr);
1866 if (i->Ain.Alu64R.op != Aalu_MOV)
1868 if (i->Ain.Alu64R.src->tag != Armi_Reg)
1870 *src = i->Ain.Alu64R.src->Armi.Reg.reg;
1871 *dst = i->Ain.Alu64R.dst;
1875 if (i->Ain.SseReRg.op != Asse_MOV)
1877 *src = i->Ain.SseReRg.src;
1878 *dst = i->Ain.SseReRg.dst;
1882 //uu if (i->Ain.AvxReRg.op != Asse_MOV)
1884 //uu *src = i->Ain.AvxReRg.src;
1885 //uu *dst = i->Ain.AvxReRg.dst;
2377 if (i->Ain.Imm64.imm64 <= 0xFFFFFULL) {
2382 if (1 & iregEnc3(i->Ain.Imm64.dst))
2384 *p++ = 0xB8 + iregEnc210(i->Ain.Imm64.dst);
2385 p = emit32(p, (UInt)i->Ain.Imm64.imm64);
2387 *p++ = toUChar(0x48 + (1 & iregEnc3(i->Ain.Imm64.dst)));
2388 *p++ = toUChar(0xB8 + iregEnc210(i->Ain.Imm64.dst));
2389 p = emit64(p, i->Ain.Imm64.imm64);
2395 if (i->Ain.Alu64R.op == Aalu_MOV) {
2396 switch (i->Ain.Alu64R.src->tag) {
2398 if (0 == (i->Ain.Alu64R.src->Armi.Imm.imm32 & ~0xFFFFF)) {
2408 if (1 & iregEnc3(i->Ain.Alu64R.dst))
2410 *p++ = 0xB8 + iregEnc210(i->Ain.Alu64R.dst);
2411 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
2413 *p++ = toUChar(0x48 + (1 & iregEnc3(i->Ain.Alu64R.dst)));
2415 *p++ = toUChar(0xC0 + iregEnc210(i->Ain.Alu64R.dst));
2416 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
2420 *p++ = rexAMode_R( i->Ain.Alu64R.src->Armi.Reg.reg,
2421 i->Ain.Alu64R.dst );
2423 p = doAMode_R(p, i->Ain.Alu64R.src->Armi.Reg.reg,
2424 i->Ain.Alu64R.dst);
2427 *p++ = rexAMode_M(i->Ain.Alu64R.dst,
2428 i->Ain.Alu64R.src->Armi.Mem.am);
2430 p = doAMode_M(p, i->Ain.Alu64R.dst,
2431 i->Ain.Alu64R.src->Armi.Mem.am);
2438 if (i->Ain.Alu64R.op == Aalu_MUL) {
2439 switch (i->Ain.Alu64R.src->tag) {
2441 *p++ = rexAMode_R( i->Ain.Alu64R.dst,
2442 i->Ain.Alu64R.src->Armi.Reg.reg);
2445 p = doAMode_R(p, i->Ain.Alu64R.dst,
2446 i->Ain.Alu64R.src->Armi.Reg.reg);
2449 *p++ = rexAMode_M(i->Ain.Alu64R.dst,
2450 i->Ain.Alu64R.src->Armi.Mem.am);
2453 p = doAMode_M(p, i->Ain.Alu64R.dst,
2454 i->Ain.Alu64R.src->Armi.Mem.am);
2457 if (fits8bits(i->Ain.Alu64R.src->Armi.Imm.imm32)) {
2458 *p++ = rexAMode_R(i->Ain.Alu64R.dst, i->Ain.Alu64R.dst);
2460 p = doAMode_R(p, i->Ain.Alu64R.dst, i->Ain.Alu64R.dst);
2461 *p++ = toUChar(0xFF & i->Ain.Alu64R.src->Armi.Imm.imm32);
2463 *p++ = rexAMode_R(i->Ain.Alu64R.dst, i->Ain.Alu64R.dst);
2465 p = doAMode_R(p, i->Ain.Alu64R.dst, i->Ain.Alu64R.dst);
2466 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
2475 switch (i->Ain.Alu64R.op) {
2494 switch (i->Ain.Alu64R.src->tag) {
2496 if (sameHReg(i->Ain.Alu64R.dst, hregAMD64_RAX())
2497 && !fits8bits(i->Ain.Alu64R.src->Armi.Imm.imm32)) {
2500 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
2502 if (fits8bits(i->Ain.Alu64R.src->Armi.Imm.imm32)) {
2503 *p++ = rexAMode_R_enc_reg( 0, i->Ain.Alu64R.dst );
2505 p = doAMode_R_enc_reg(p, subopc_imm, i->Ain.Alu64R.dst);
2506 *p++ = toUChar(0xFF & i->Ain.Alu64R.src->Armi.Imm.imm32);
2508 *p++ = rexAMode_R_enc_reg( 0, i->Ain.Alu64R.dst);
2510 p = doAMode_R_enc_reg(p, subopc_imm, i->Ain.Alu64R.dst);
2511 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
2515 *p++ = rexAMode_R( i->Ain.Alu64R.src->Armi.Reg.reg,
2516 i->Ain.Alu64R.dst);
2518 p = doAMode_R(p, i->Ain.Alu64R.src->Armi.Reg.reg,
2519 i->Ain.Alu64R.dst);
2522 *p++ = rexAMode_M( i->Ain.Alu64R.dst,
2523 i->Ain.Alu64R.src->Armi.Mem.am);
2525 p = doAMode_M(p, i->Ain.Alu64R.dst,
2526 i->Ain.Alu64R.src->Armi.Mem.am);
2535 if (i->Ain.Alu64M.op == Aalu_MOV) {
2536 switch (i->Ain.Alu64M.src->tag) {
2538 *p++ = rexAMode_M(i->Ain.Alu64M.src->Ari.Reg.reg,
2539 i->Ain.Alu64M.dst);
2541 p = doAMode_M(p, i->Ain.Alu64M.src->Ari.Reg.reg,
2542 i->Ain.Alu64M.dst);
2545 *p++ = rexAMode_M_enc(0, i->Ain.Alu64M.dst);
2547 p = doAMode_M_enc(p, 0, i->Ain.Alu64M.dst);
2548 p = emit32(p, i->Ain.Alu64M.src->Ari.Imm.imm32);
2558 switch (i->Ain.Sh64.op) {
2564 if (i->Ain.Sh64.src == 0) {
2565 *p++ = rexAMode_R_enc_reg(0, i->Ain.Sh64.dst);
2567 p = doAMode_R_enc_reg(p, subopc, i->Ain.Sh64.dst);
2570 *p++ = rexAMode_R_enc_reg(0, i->Ain.Sh64.dst);
2572 p = doAMode_R_enc_reg(p, subopc, i->Ain.Sh64.dst);
2573 *p++ = (UChar)(i->Ain.Sh64.src);
2580 *p++ = rexAMode_R_enc_reg(0, i->Ain.Test64.dst);
2582 p = doAMode_R_enc_reg(p, 0, i->Ain.Test64.dst);
2583 p = emit32(p, i->Ain.Test64.imm32);
2587 if (i->Ain.Unary64.op == Aun_NOT) {
2588 *p++ = rexAMode_R_enc_reg(0, i->Ain.Unary64.dst);
2590 p = doAMode_R_enc_reg(p, 2, i->Ain.Unary64.dst);
2593 if (i->Ain.Unary64.op == Aun_NEG) {
2594 *p++ = rexAMode_R_enc_reg(0, i->Ain.Unary64.dst);
2596 p = doAMode_R_enc_reg(p, 3, i->Ain.Unary64.dst);
2602 *p++ = rexAMode_M(i->Ain.Lea64.dst, i->Ain.Lea64.am);
2604 p = doAMode_M(p, i->Ain.Lea64.dst, i->Ain.Lea64.am);
2610 switch (i->Ain.Alu32R.op) {
2625 switch (i->Ain.Alu32R.src->tag) {
2627 if (sameHReg(i->Ain.Alu32R.dst, hregAMD64_RAX())
2628 && !fits8bits(i->Ain.Alu32R.src->Armi.Imm.imm32)) {
2631 p = emit32(p, i->Ain.Alu32R.src->Armi.Imm.imm32);
2633 if (fits8bits(i->Ain.Alu32R.src->Armi.Imm.imm32)) {
2634 rex = clearWBit( rexAMode_R_enc_reg( 0, i->Ain.Alu32R.dst ) );
2637 p = doAMode_R_enc_reg(p, subopc_imm, i->Ain.Alu32R.dst);
2638 *p++ = toUChar(0xFF & i->Ain.Alu32R.src->Armi.Imm.imm32);
2640 rex = clearWBit( rexAMode_R_enc_reg( 0, i->Ain.Alu32R.dst) );
2643 p = doAMode_R_enc_reg(p, subopc_imm, i->Ain.Alu32R.dst);
2644 p = emit32(p, i->Ain.Alu32R.src->Armi.Imm.imm32);
2649 rexAMode_R( i->Ain.Alu32R.src->Armi.Reg.reg,
2650 i->Ain.Alu32R.dst) );
2653 p = doAMode_R(p, i->Ain.Alu32R.src->Armi.Reg.reg,
2654 i->Ain.Alu32R.dst);
2658 rexAMode_M( i->Ain.Alu32R.dst,
2659 i->Ain.Alu32R.src->Armi.Mem.am) );
2662 p = doAMode_M(p, i->Ain.Alu32R.dst,
2663 i->Ain.Alu32R.src->Armi.Mem.am);
2671 subopc = i->Ain.MulL.syned ? 5 : 4;
2672 switch (i->Ain.MulL.src->tag) {
2674 *p++ = rexAMode_M_enc(0, i->Ain.MulL.src->Arm.Mem.am);
2676 p = doAMode_M_enc(p, subopc, i->Ain.MulL.src->Arm.Mem.am);
2679 *p++ = rexAMode_R_enc_reg(0, i->Ain.MulL.src->Arm.Reg.reg);
2681 p = doAMode_R_enc_reg(p, subopc, i->Ain.MulL.src->Arm.Reg.reg);
2689 subopc = i->Ain.Div.syned ? 7 : 6;
2690 if (i->Ain.Div.sz == 4) {
2691 switch (i->Ain.Div.src->tag) {
2696 p = doAMode_M_enc(p, subopc, i->Ain.Div.src->Arm.Mem.am);
2700 rexAMode_R_enc_reg(0, i->Ain.Div.src->Arm.Reg.reg));
2702 p = doAMode_R_enc_reg(p, subopc, i->Ain.Div.src->Arm.Reg.reg);
2708 if (i->Ain.Div.sz == 8) {
2709 switch (i->Ain.Div.src->tag) {
2711 *p++ = rexAMode_M_enc(0, i->Ain.Div.src->Arm.Mem.am);
2713 p = doAMode_M_enc(p, subopc, i->Ain.Div.src->Arm.Mem.am);
2716 *p++ = rexAMode_R_enc_reg(0, i->Ain.Div.src->Arm.Reg.reg);
2718 p = doAMode_R_enc_reg(p, subopc, i->Ain.Div.src->Arm.Reg.reg);
2727 switch (i->Ain.Push.src->tag) {
2730 rexAMode_M_enc(0, i->Ain.Push.src->Armi.Mem.am));
2732 p = doAMode_M_enc(p, 6, i->Ain.Push.src->Armi.Mem.am);
2736 p = emit32(p, i->Ain.Push.src->Armi.Imm.imm32);
2739 *p++ = toUChar(0x40 + (1 & iregEnc3(i->Ain.Push.src->Armi.Reg.reg)));
2740 *p++ = toUChar(0x50 + iregEnc210(i->Ain.Push.src->Armi.Reg.reg));
2752 if (i->Ain.Call.cond == Acc_ALWAYS/*call always happens*/
2753 || i->Ain.Call.rloc.pri == RLPri_None/*no fixup action*/) {
2756 Bool shortImm = fitsIn32Bits(i->Ain.Call.target);
2757 if (i->Ain.Call.cond != Acc_ALWAYS) {
2758 *p++ = toUChar(0x70 + (0xF & (i->Ain.Call.cond ^ 1)));
2767 p = emit32(p, (UInt)i->Ain.Call.target);
2772 p = emit64(p, i->Ain.Call.target);
2796 *p++ = toUChar(0x70 + (0xF & (i->Ain.Call.cond ^ 1)));
2802 p = emit64(p, i->Ain.Call.target);
2820 switch (i->Ain.Call.rloc.pri) {
2873 if (i->Ain.XDirect.cond != Acc_ALWAYS) {
2875 *p++ = toUChar(0x70 + (0xF & (i->Ain.XDirect.cond ^ 1)));
2881 if (fitsIn32Bits(i->Ain.XDirect.dstGA)) {
2887 p = emit32(p, (UInt)i->Ain.XDirect.dstGA);
2892 p = emit64(p, i->Ain.XDirect.dstGA);
2896 *p++ = rexAMode_M(r11, i->Ain.XDirect.amRIP);
2898 p = doAMode_M(p, r11, i->Ain.XDirect.amRIP);
2909 = i->Ain.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP
2919 if (i->Ain.XDirect.cond != Acc_ALWAYS) {
2941 if (i->Ain.XIndir.cond != Acc_ALWAYS) {
2943 *p++ = toUChar(0x70 + (0xF & (i->Ain.XIndir.cond ^ 1)));
2949 *p++ = rexAMode_M(i->Ain.XIndir.dstGA, i->Ain.XIndir.amRIP);
2951 p = doAMode_M(p, i->Ain.XIndir.dstGA, i->Ain.XIndir.amRIP);
2974 if (i->Ain.XIndir.cond != Acc_ALWAYS) {
2988 if (i->Ain.XAssisted.cond != Acc_ALWAYS) {
2990 *p++ = toUChar(0x70 + (0xF & (i->Ain.XAssisted.cond ^ 1)));
2996 *p++ = rexAMode_M(i->Ain.XAssisted.dstGA, i->Ain.XAssisted.amRIP);
2998 p = doAMode_M(p, i->Ain.XAssisted.dstGA, i->Ain.XAssisted.amRIP);
3003 switch (i->Ain.XAssisted.jk) {
3021 ppIRJumpKind(i->Ain.XAssisted.jk);
3037 if (i->Ain.XAssisted.cond != Acc_ALWAYS) {
3046 vassert(i->Ain.CMov64.cond != Acc_ALWAYS);
3047 *p++ = rexAMode_R(i->Ain.CMov64.dst, i->Ain.CMov64.src);
3049 *p++ = toUChar(0x40 + (0xF & i->Ain.CMov64.cond));
3050 p = doAMode_R(p, i->Ain.CMov64.dst, i->Ain.CMov64.src);
3054 vassert(i->Ain.CLoad.cond != Acc_ALWAYS);
3057 vassert(i->Ain.CLoad.szB == 4 || i->Ain.CLoad.szB == 8);
3063 *p++ = toUChar(0x70 + (0xF & (i->Ain.CLoad.cond ^ 1)));
3070 rex = rexAMode_M(i->Ain.CLoad.dst, i->Ain.CLoad.addr);
3071 *p++ = i->Ain.CLoad.szB == 4 ? clearWBit(rex) : rex;
3073 p = doAMode_M(p, i->Ain.CLoad.dst, i->Ain.CLoad.addr);
3085 vassert(i->Ain.CStore.cond != Acc_ALWAYS);
3088 vassert(i->Ain.CStore.szB == 4 || i->Ain.CStore.szB == 8);
3094 *p++ = toUChar(0x70 + (0xF & (i->Ain.CStore.cond ^ 1)));
3099 rex = rexAMode_M(i->Ain.CStore.src, i->Ain.CStore.addr);
3100 *p++ = i->Ain.CStore.szB == 4 ? clearWBit(rex) : rex;
3102 p = doAMode_M(p, i->Ain.CStore.src, i->Ain.CStore.addr);
3114 if (i->Ain.MovxLQ.syned) {
3116 *p++ = rexAMode_R(i->Ain.MovxLQ.dst, i->Ain.MovxLQ.src);
3118 p = doAMode_R(p, i->Ain.MovxLQ.dst, i->Ain.MovxLQ.src);
3123 rexAMode_R(i->Ain.MovxLQ.src, i->Ain.MovxLQ.dst));
3125 p = doAMode_R(p, i->Ain.MovxLQ.src, i->Ain.MovxLQ.dst);
3130 if (i->Ain.LoadEX.szSmall == 1 && !i->Ain.LoadEX.syned) {
3132 *p++ = rexAMode_M(i->Ain.LoadEX.dst, i->Ain.LoadEX.src);
3135 p = doAMode_M(p, i->Ain.LoadEX.dst, i->Ain.LoadEX.src);
3138 if (i->Ain.LoadEX.szSmall == 2 && !i->Ain.LoadEX.syned) {
3140 *p++ = rexAMode_M(i->Ain.LoadEX.dst, i->Ain.LoadEX.src);
3143 p = doAMode_M(p, i->Ain.LoadEX.dst, i->Ain.LoadEX.src);
3146 if (i->Ain.LoadEX.szSmall == 4 && !i->Ain.LoadEX.syned) {
3153 rexAMode_M(i->Ain.LoadEX.dst, i->Ain.LoadEX.src));
3155 p = doAMode_M(p, i->Ain.LoadEX.dst, i->Ain.LoadEX.src);
3166 reg = iregEnc3210(i->Ain.Set64.dst);
3179 *p++ = toUChar(0x90 + (0x0F & i->Ain.Set64.cond));
3184 *p++ = rexAMode_R(i->Ain.Bsfr64.dst, i->Ain.Bsfr64.src);
3186 if (i->Ain.Bsfr64.isFwds) {
3191 p = doAMode_R(p, i->Ain.Bsfr64.dst, i->Ain.Bsfr64.src);
3202 if (i->Ain.ACAS.sz == 2) *p++ = 0x66;
3208 rex = rexAMode_M( hregAMD64_RBX(), i->Ain.ACAS.addr );
3209 if (i->Ain.ACAS.sz != 8)
3214 if (i->Ain.ACAS.sz == 1) *p++ = 0xB0; else *p++ = 0xB1;
3215 p = doAMode_M(p, hregAMD64_RBX(), i->Ain.ACAS.addr);
3224 rex = rexAMode_M_enc(1, i->Ain.ACAS.addr );
3225 if (i->Ain.ACAS.sz != 8)
3230 p = doAMode_M_enc(p, 1, i->Ain.DACAS.addr);
3234 vassert(i->Ain.A87Free.nregs > 0 && i->Ain.A87Free.nregs <= 7);
3235 for (j = 0; j < i->Ain.A87Free.nregs; j++) {
3241 vassert(i->Ain.A87PushPop.szB == 8 || i->Ain.A87PushPop.szB == 4);
3242 if (i->Ain.A87PushPop.isPush) {
3245 rexAMode_M_enc(0, i->Ain.A87PushPop.addr) );
3246 *p++ = i->Ain.A87PushPop.szB == 4 ? 0xD9 : 0xDD;
3247 p = doAMode_M_enc(p, 0/*subopcode*/, i->Ain.A87PushPop.addr);
3251 rexAMode_M_enc(3, i->Ain.A87PushPop.addr) );
3252 *p++ = i->Ain.A87PushPop.szB == 4 ? 0xD9 : 0xDD;
3253 p = doAMode_M_enc(p, 3/*subopcode*/, i->Ain.A87PushPop.addr);
3259 switch (i->Ain.A87FpOp.op) {
3294 rexAMode_M_enc(5, i->Ain.A87LdCW.addr) );
3296 p = doAMode_M_enc(p, 5/*subopcode*/, i->Ain.A87LdCW.addr);
3301 rexAMode_M_enc(7, i->Ain.A87StSW.addr) );
3303 p = doAMode_M_enc(p, 7/*subopcode*/, i->Ain.A87StSW.addr);
3307 if (i->Ain.Store.sz == 2) {
3313 *p++ = clearWBit( rexAMode_M( i->Ain.Store.src, i->Ain.Store.dst) );
3315 p = doAMode_M(p, i->Ain.Store.src, i->Ain.Store.dst);
3318 if (i->Ain.Store.sz == 4) {
3319 *p++ = clearWBit( rexAMode_M( i->Ain.Store.src, i->Ain.Store.dst) );
3321 p = doAMode_M(p, i->Ain.Store.src, i->Ain.Store.dst);
3324 if (i->Ain.Store.sz == 1) {
3328 *p++ = clearWBit( rexAMode_M( i->Ain.Store.src, i->Ain.Store.dst) );
3330 p = doAMode_M(p, i->Ain.Store.src, i->Ain.Store.dst);
3336 *p++ = clearWBit(rexAMode_M_enc(0, i->Ain.LdMXCSR.addr));
3339 p = doAMode_M_enc(p, 2/*subopcode*/, i->Ain.LdMXCSR.addr);
3345 if (i->Ain.SseUComIS.sz == 8) {
3349 vassert(i->Ain.SseUComIS.sz == 4);
3352 rexAMode_R_enc_enc( vregEnc3210(i->Ain.SseUComIS.srcL),
3353 vregEnc3210(i->Ain.SseUComIS.srcR) ));
3356 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.SseUComIS.srcL),
3357 vregEnc3210(i->Ain.SseUComIS.srcR) );
3361 *p++ = toUChar(0x40 + (1 & iregEnc3(i->Ain.SseUComIS.dst)));
3362 *p++ = toUChar(0x58 + iregEnc210(i->Ain.SseUComIS.dst));
3367 rex = rexAMode_R_enc_reg( vregEnc3210(i->Ain.SseSI2SF.dst),
3368 i->Ain.SseSI2SF.src );
3369 *p++ = toUChar(i->Ain.SseSI2SF.szD==4 ? 0xF3 : 0xF2);
3370 *p++ = toUChar(i->Ain.SseSI2SF.szS==4 ? clearWBit(rex) : rex);
3373 p = doAMode_R_enc_reg( p, vregEnc3210(i->Ain.SseSI2SF.dst),
3374 i->Ain.SseSI2SF.src );
3379 rex = rexAMode_R_reg_enc( i->Ain.SseSF2SI.dst,
3380 vregEnc3210(i->Ain.SseSF2SI.src) );
3381 *p++ = toUChar(i->Ain.SseSF2SI.szS==4 ? 0xF3 : 0xF2);
3382 *p++ = toUChar(i->Ain.SseSF2SI.szD==4 ? clearWBit(rex) : rex);
3385 p = doAMode_R_reg_enc( p, i->Ain.SseSF2SI.dst,
3386 vregEnc3210(i->Ain.SseSF2SI.src) );
3391 *p++ = toUChar(i->Ain.SseSDSS.from64 ? 0xF2 : 0xF3);
3393 rexAMode_R_enc_enc( vregEnc3210(i->Ain.SseSDSS.dst),
3394 vregEnc3210(i->Ain.SseSDSS.src) ));
3397 p = doAMode_R_enc_enc( p, vregEnc3210(i->Ain.SseSDSS.dst),
3398 vregEnc3210(i->Ain.SseSDSS.src) );
3402 if (i->Ain.SseLdSt.sz == 8) {
3405 if (i->Ain.SseLdSt.sz == 4) {
3408 if (i->Ain.SseLdSt.sz != 16) {
3412 rexAMode_M_enc(vregEnc3210(i->Ain.SseLdSt.reg),
3413 i->Ain.SseLdSt.addr));
3415 *p++ = toUChar(i->Ain.SseLdSt.isLoad ? 0x10 : 0x11);
3416 p = doAMode_M_enc(p, vregEnc3210(i->Ain.SseLdSt.reg),
3417 i->Ain.SseLdSt.addr);
3421 vassert(i->Ain.SseLdzLO.sz == 4 || i->Ain.SseLdzLO.sz == 8);
3423 *p++ = toUChar(i->Ain.SseLdzLO.sz==4 ? 0xF3 : 0xF2);
3425 rexAMode_M_enc(vregEnc3210(i->Ain.SseLdzLO.reg),
3426 i->Ain.SseLdzLO.addr));
3429 p = doAMode_M_enc(p, vregEnc3210(i->Ain.SseLdzLO.reg),
3430 i->Ain.SseLdzLO.addr);
3436 rexAMode_R_enc_enc( vregEnc3210(i->Ain.Sse32Fx4.dst),
3437 vregEnc3210(i->Ain.Sse32Fx4.src) ));
3439 switch (i->Ain.Sse32Fx4.op) {
3455 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.Sse32Fx4.dst),
3456 vregEnc3210(i->Ain.Sse32Fx4.src) );
3465 rexAMode_R_enc_enc( vregEnc3210(i->Ain.Sse64Fx2.dst),
3466 vregEnc3210(i->Ain.Sse64Fx2.src) ));
3468 switch (i->Ain.Sse64Fx2.op) {
3482 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.Sse64Fx2.dst),
3483 vregEnc3210(i->Ain.Sse64Fx2.src) );
3492 rexAMode_R_enc_enc( vregEnc3210(i->Ain.Sse32FLo.dst),
3493 vregEnc3210(i->Ain.Sse32FLo.src) ));
3495 switch (i->Ain.Sse32FLo.op) {
3511 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.Sse32FLo.dst),
3512 vregEnc3210(i->Ain.Sse32FLo.src) );
3521 rexAMode_R_enc_enc( vregEnc3210(i->Ain.Sse64FLo.dst),
3522 vregEnc3210(i->Ain.Sse64FLo.src) ));
3524 switch (i->Ain.Sse64FLo.op) {
3538 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.Sse64FLo.dst),
3539 vregEnc3210(i->Ain.Sse64FLo.src) );
3548 rexAMode_R_enc_enc( vregEnc3210(i->Ain.SseReRg.dst),
3549 vregEnc3210(i->Ain.SseReRg.src) ));
3551 switch (i->Ain.SseReRg.op) {
3609 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.SseReRg.dst),
3610 vregEnc3210(i->Ain.SseReRg.src) );
3616 *p++ = toUChar(0x70 + (i->Ain.SseCMov.cond ^ 1));
3622 rexAMode_R_enc_enc( vregEnc3210(i->Ain.SseCMov.dst),
3623 vregEnc3210(i->Ain.SseCMov.src) ));
3626 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.SseCMov.dst),
3627 vregEnc3210(i->Ain.SseCMov.src) );
3636 rexAMode_R_enc_enc( vregEnc3210(i->Ain.SseShuf.dst),
3637 vregEnc3210(i->Ain.SseShuf.src) ));
3640 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.SseShuf.dst),
3641 vregEnc3210(i->Ain.SseShuf.src) );
3642 *p++ = (UChar)(i->Ain.SseShuf.order);
3646 //uu UInt vex = vexAMode_M( dvreg2ireg(i->Ain.AvxLdSt.reg),
3647 //uu i->Ain.AvxLdSt.addr );
3649 //uu *p++ = toUChar(i->Ain.AvxLdSt.isLoad ? 0x10 : 0x11);
3650 //uu p = doAMode_M(p, dvreg2ireg(i->Ain.AvxLdSt.reg), i->Ain.AvxLdSt.addr);
3676 rex = clearWBit(rexAMode_M_enc(1, i->Ain.EvCheck.amCounter));
3679 p = doAMode_M_enc(p, 1, i->Ain.EvCheck.amCounter);
3689 rex = clearWBit(rexAMode_M_enc(4, i->Ain.EvCheck.amFailAddr));
3692 p = doAMode_M_enc(p, 4, i->Ain.EvCheck.amFailAddr);
