Lines Matching defs:env
115 static HReg lookupIRTemp ( ISelEnv* env, IRTemp tmp )
118 vassert(tmp < env->n_vregmap);
119 return env->vregmap[tmp];
123 ISelEnv* env, IRTemp tmp )
126 vassert(tmp < env->n_vregmap);
127 vassert(! hregIsInvalid(env->vregmapHI[tmp]));
128 *vrLO = env->vregmap[tmp];
129 *vrHI = env->vregmapHI[tmp];
132 static void addInstr ( ISelEnv* env, ARM64Instr* instr )
134 addHInstr(env->code, instr);
141 static HReg newVRegI ( ISelEnv* env )
143 HReg reg = mkHReg(True/*virtual reg*/, HRcInt64, 0, env->vreg_ctr);
144 env->vreg_ctr++;
148 static HReg newVRegD ( ISelEnv* env )
150 HReg reg = mkHReg(True/*virtual reg*/, HRcFlt64, 0, env->vreg_ctr);
151 env->vreg_ctr++;
155 static HReg newVRegV ( ISelEnv* env )
157 HReg reg = mkHReg(True/*virtual reg*/, HRcVec128, 0, env->vreg_ctr);
158 env->vreg_ctr++;
178 static ARM64AMode* iselIntExpr_AMode_wrk ( ISelEnv* env,
180 static ARM64AMode* iselIntExpr_AMode ( ISelEnv* env,
183 static ARM64RIA* iselIntExpr_RIA_wrk ( ISelEnv* env, IRExpr* e );
184 static ARM64RIA* iselIntExpr_RIA ( ISelEnv* env, IRExpr* e );
186 static ARM64RIL* iselIntExpr_RIL_wrk ( ISelEnv* env, IRExpr* e );
187 static ARM64RIL* iselIntExpr_RIL ( ISelEnv* env, IRExpr* e );
189 static ARM64RI6* iselIntExpr_RI6_wrk ( ISelEnv* env, IRExpr* e );
190 static ARM64RI6* iselIntExpr_RI6 ( ISelEnv* env, IRExpr* e );
192 static ARM64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e );
193 static ARM64CondCode iselCondCode ( ISelEnv* env, IRExpr* e );
195 static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e );
196 static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e );
199 ISelEnv* env, IRExpr* e );
201 ISelEnv* env, IRExpr* e );
203 static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e );
204 static HReg iselDblExpr ( ISelEnv* env, IRExpr* e );
206 static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e );
207 static HReg iselFltExpr ( ISelEnv* env, IRExpr* e );
209 static HReg iselF16Expr_wrk ( ISelEnv* env, IRExpr* e );
210 static HReg iselF16Expr ( ISelEnv* env, IRExpr* e );
212 static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e );
213 static HReg iselV128Expr ( ISelEnv* env, IRExpr* e );
216 ISelEnv* env, IRExpr* e );
218 ISelEnv* env, IRExpr* e );
262 static HReg mk_baseblock_128bit_access_addr ( ISelEnv* env, UInt off )
265 HReg r = newVRegI(env);
266 addInstr(env, ARM64Instr_Arith(r, hregARM64_X21(),
278 static HReg widen_z_32_to_64 ( ISelEnv* env, HReg src )
280 HReg dst = newVRegI(env);
282 addInstr(env, ARM64Instr_Logic(dst, src, mask, ARM64lo_AND));
288 static HReg widen_s_16_to_64 ( ISelEnv* env, HReg src )
290 HReg dst = newVRegI(env);
292 addInstr(env, ARM64Instr_Shift(dst, src, n48, ARM64sh_SHL));
293 addInstr(env, ARM64Instr_Shift(dst, dst, n48, ARM64sh_SAR));
299 static HReg widen_z_16_to_64 ( ISelEnv* env, HReg src )
301 HReg dst = newVRegI(env);
303 addInstr(env, ARM64Instr_Shift(dst, src, n48, ARM64sh_SHL));
304 addInstr(env, ARM64Instr_Shift(dst, dst, n48, ARM64sh_SHR));
310 static HReg widen_s_32_to_64 ( ISelEnv* env, HReg src )
312 HReg dst = newVRegI(env);
314 addInstr(env, ARM64Instr_Shift(dst, src, n32, ARM64sh_SHL));
315 addInstr(env, ARM64Instr_Shift(dst, dst, n32, ARM64sh_SAR));
321 static HReg widen_s_8_to_64 ( ISelEnv* env, HReg src )
323 HReg dst = newVRegI(env);
325 addInstr(env, ARM64Instr_Shift(dst, src, n56, ARM64sh_SHL));
326 addInstr(env, ARM64Instr_Shift(dst, dst, n56, ARM64sh_SAR));
330 static HReg widen_z_8_to_64 ( ISelEnv* env, HReg src )
332 HReg dst = newVRegI(env);
334 addInstr(env, ARM64Instr_Shift(dst, src, n56, ARM64sh_SHL));
335 addInstr(env, ARM64Instr_Shift(dst, dst, n56, ARM64sh_SHR));
364 env->previous_rm.) If 'mode' is a single IR temporary 't' and
365 env->previous_rm is also just 't', then the setting is skipped.
381 void set_FPCR_rounding_mode ( ISelEnv* env, IRExpr* mode )
383 vassert(typeOfIRExpr(env->type_env,mode) == Ity_I32);
386 if (env->previous_rm
387 && env->previous_rm->tag == Iex_RdTmp
389 && env->previous_rm->Iex.RdTmp.tmp == mode->Iex.RdTmp.tmp) {
391 vassert(typeOfIRExpr(env->type_env, env->previous_rm) == Ity_I32);
396 env->previous_rm = mode;
415 HReg irrm = iselIntExpr_R(env, mode);
416 HReg tL = newVRegI(env);
417 HReg tR = newVRegI(env);
418 HReg t3 = newVRegI(env);
430 addInstr(env, ARM64Instr_Shift(tL, irrm, ARM64RI6_I6(1), ARM64sh_SHL));
431 addInstr(env, ARM64Instr_Shift(tR, irrm, ARM64RI6_I6(1), ARM64sh_SHR));
432 addInstr(env, ARM64Instr_Logic(tL, tL, ril_two, ARM64lo_AND));
433 addInstr(env, ARM64Instr_Logic(tR, tR, ril_one, ARM64lo_AND));
434 addInstr(env, ARM64Instr_Logic(t3, tL, ARM64RIL_R(tR), ARM64lo_OR));
435 addInstr(env, ARM64Instr_Shift(t3, t3, ARM64RI6_I6(22), ARM64sh_SHL));
436 addInstr(env, ARM64Instr_FPCR(True/*toFPCR*/, t3));
478 ISelEnv* env,
578 r_vecRetAddr = newVRegI(env);
579 addInstr(env, ARM64Instr_AddToSP(-16));
580 addInstr(env, ARM64Instr_FromSP(r_vecRetAddr));
644 aTy = typeOfIRExpr(env->type_env, args[i]);
650 addInstr(env, ARM64Instr_MovI( argregs[nextArgReg],
651 iselIntExpr_R(env, args[i]) ));
656 addInstr(env, ARM64Instr_MovI( argregs[nextArgReg],
683 aTy = typeOfIRExpr(env->type_env, args[i]);
689 tmpregs[nextArgReg] = iselIntExpr_R(env, args[i]);
717 cc = iselCondCode( env, guard );
726 addInstr( env, ARM64Instr_MovI( argregs[i], tmpregs[i] ) );
774 addInstr(env, ARM64Instr_Call( cc, target, nextArgReg, *retloc ));
844 ARM64AMode* iselIntExpr_AMode ( ISelEnv* env, IRExpr* e, IRType dty )
846 ARM64AMode* am = iselIntExpr_AMode_wrk(env, e, dty);
852 ARM64AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, IRExpr* e, IRType dty )
854 IRType ty = typeOfIRExpr(env->type_env,e);
880 HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg1);
895 HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg1);
903 HReg reg1 = iselIntExpr_R(env, e->Iex.Binop.arg1);
904 HReg reg2 = iselIntExpr_R(env, e->Iex.Binop.arg2);
910 HReg reg = iselIntExpr_R(env, e);
919 static ARM64RIA* iselIntExpr_RIA ( ISelEnv* env, IRExpr* e )
921 ARM64RIA* ri = iselIntExpr_RIA_wrk(env, e);
938 static ARM64RIA* iselIntExpr_RIA_wrk ( ISelEnv* env, IRExpr* e )
940 IRType ty = typeOfIRExpr(env->type_env,e);
960 HReg r = iselIntExpr_R ( env, e );
1182 static ARM64RIL* iselIntExpr_RIL ( ISelEnv* env, IRExpr* e )
1184 ARM64RIL* ri = iselIntExpr_RIL_wrk(env, e);
1202 static ARM64RIL* iselIntExpr_RIL_wrk ( ISelEnv* env, IRExpr* e )
1204 IRType ty = typeOfIRExpr(env->type_env,e);
1232 HReg r = iselIntExpr_R ( env, e );
1242 static ARM64RI6* iselIntExpr_RI6 ( ISelEnv* env, IRExpr* e )
1244 ARM64RI6* ri = iselIntExpr_RI6_wrk(env, e);
1261 static ARM64RI6* iselIntExpr_RI6_wrk ( ISelEnv* env, IRExpr* e )
1263 IRType ty = typeOfIRExpr(env->type_env,e);
1283 HReg r = iselIntExpr_R ( env, e );
1295 static ARM64CondCode iselCondCode ( ISelEnv* env, IRExpr* e )
1297 ARM64CondCode cc = iselCondCode_wrk(env,e);
1302 static ARM64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e )
1305 vassert(typeOfIRExpr(env->type_env,e) == Ity_I1);
1309 HReg rTmp = lookupIRTemp(env, e->Iex.RdTmp.tmp);
1313 addInstr(env, ARM64Instr_Test(rTmp, one));
1320 ARM64CondCode cc = iselCondCode(env, e->Iex.Unop.arg);
1332 HReg rTmp = iselIntExpr_R(env, e->Iex.Unop.arg);
1335 addInstr(env, ARM64Instr_Test(rTmp, one));
1343 HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg);
1345 addInstr(env, ARM64Instr_Test(r1, xFF));
1353 HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg);
1355 addInstr(env, ARM64Instr_Test(r1, xFFFF));
1363 HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg);
1365 addInstr(env, ARM64Instr_Cmp(r1, zero, True/*is64*/));
1373 HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg);
1375 addInstr(env, ARM64Instr_Cmp(r1, zero, False/*!is64*/));
1387 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1388 ARM64RIA* argR = iselIntExpr_RIA(env, e->Iex.Binop.arg2);
1389 addInstr(env, ARM64Instr_Cmp(argL, argR, True/*is64*/));
1409 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1410 ARM64RIA* argR = iselIntExpr_RIA(env, e->Iex.Binop.arg2);
1411 addInstr(env, ARM64Instr_Cmp(argL, argR, False/*!is64*/));
1430 static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e )
1432 HReg r = iselIntExpr_R_wrk(env, e);
1443 static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
1445 IRType ty = typeOfIRExpr(env->type_env,e);
1452 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
1457 HReg dst = newVRegI(env);
1463 ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty );
1464 addInstr(env, ARM64Instr_LdSt64(True/*isLoad*/, dst, amode));
1468 ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty );
1469 addInstr(env, ARM64Instr_LdSt32(True/*isLoad*/, dst, amode));
1473 ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty );
1474 addInstr(env, ARM64Instr_LdSt16(True/*isLoad*/, dst, amode));
1478 ARM64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr, ty );
1479 addInstr(env, ARM64Instr_LdSt8(True/*isLoad*/, dst, amode));
1498 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1499 HReg dst = newVRegI(env);
1500 addInstr(env, ARM64Instr_Unary(dst, argR, ARM64un_NEG));
1514 HReg dst = newVRegI(env);
1515 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1516 ARM64RIA* argR = iselIntExpr_RIA(env, e->Iex.Binop.arg2);
1517 addInstr(env, ARM64Instr_Arith(dst, argL, argR, isAdd));
1530 HReg dst = newVRegI(env);
1531 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1532 ARM64RIL* argR = iselIntExpr_RIL(env, e->Iex.Binop.arg2);
1533 addInstr(env, ARM64Instr_Logic(dst, argL, argR, lop));
1546 HReg dst = newVRegI(env);
1547 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1548 ARM64RI6* argR = iselIntExpr_RI6(env, e->Iex.Binop.arg2);
1549 addInstr(env, ARM64Instr_Shift(dst, argL, argR, sop));
1555 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1556 ARM64RI6* argR = iselIntExpr_RI6(env, e->Iex.Binop.arg2);
1557 HReg dst = zx ? widen_z_32_to_64(env, argL)
1558 : widen_s_32_to_64(env, argL);
1559 addInstr(env, ARM64Instr_Shift(dst, dst, argR, ARM64sh_SHR));
1567 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1568 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1569 HReg dst = newVRegI(env);
1570 addInstr(env, ARM64Instr_Mul(dst, argL, argR, ARM64mul_PLAIN));
1577 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1578 HReg extL = (isS ? widen_s_32_to_64 : widen_z_32_to_64)(env, argL);
1579 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1580 HReg extR = (isS ? widen_s_32_to_64 : widen_z_32_to_64)(env, argR);
1581 HReg dst = newVRegI(env);
1582 addInstr(env, ARM64Instr_Mul(dst, extL, extR, ARM64mul_PLAIN));
1589 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1590 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1591 HReg dst = newVRegI(env);
1592 addInstr(env, ARM64Instr_Cmp(argL, ARM64RIA_R(argR), False/*!is64*/));
1593 addInstr(env, ARM64Instr_CSel(dst, argL, argR, ARM64cc_CS));
1598 HReg hi32s = iselIntExpr_R(env, e->Iex.Binop.arg1);
1599 HReg lo32s = iselIntExpr_R(env, e->Iex.Binop.arg2);
1600 HReg lo32 = widen_z_32_to_64(env, lo32s);
1601 HReg hi32 = newVRegI(env);
1602 addInstr(env, ARM64Instr_Shift(hi32, hi32s, ARM64RI6_I6(32),
1604 addInstr(env, ARM64Instr_Logic(hi32, hi32, ARM64RIL_R(lo32),
1611 HReg dL = (isD ? iselDblExpr : iselFltExpr)(env, e->Iex.Binop.arg1);
1612 HReg dR = (isD ? iselDblExpr : iselFltExpr)(env, e->Iex.Binop.arg2);
1613 HReg dst = newVRegI(env);
1614 HReg imm = newVRegI(env);
1617 addInstr(env, (isD ? ARM64Instr_VCmpD : ARM64Instr_VCmpS)(dL, dR));
1618 addInstr(env, ARM64Instr_Imm64(dst, 0));
1619 addInstr(env, ARM64Instr_Imm64(imm, 0x40)); // 0x40 = Ircr_EQ
1620 addInstr(env, ARM64Instr_CSel(dst, imm, dst, ARM64cc_EQ));
1621 addInstr(env, ARM64Instr_Imm64(imm, 0x01)); // 0x01 = Ircr_LT
1622 addInstr(env, ARM64Instr_CSel(dst, imm, dst, ARM64cc_MI));
1623 addInstr(env, ARM64Instr_Imm64(imm, 0x00)); // 0x00 = Ircr_GT
1624 addInstr(env, ARM64Instr_CSel(dst, imm, dst, ARM64cc_GT));
1625 addInstr(env, ARM64Instr_Imm64(imm, 0x45)); // 0x45 = Ircr_UN
1626 addInstr(env, ARM64Instr_CSel(dst, imm, dst, ARM64cc_VS));
1679 (env, e->Iex.Binop.arg2);
1680 HReg dst = newVRegI(env);
1681 addInstr(env, ARM64Instr_VCvtF2I(cvt_op, dst, src, armrm));
1702 HReg regL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1703 HReg regR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1704 HReg res = newVRegI(env);
1705 addInstr(env, ARM64Instr_MovI(hregARM64_X0(), regL));
1706 addInstr(env, ARM64Instr_MovI(hregARM64_X1(), regR));
1707 addInstr(env, ARM64Instr_Call( ARM64cc_AL, (Addr)fn,
1709 addInstr(env, ARM64Instr_MovI(res, hregARM64_X0()));
1724 HReg src = iselIntExpr_R(env, arg);
1725 HReg dst = widen_z_16_to_64(env, src);
1733 HReg dst = newVRegI(env);
1735 = iselIntExpr_AMode(env, arg->Iex.Load.addr, Ity_I32);
1736 addInstr(env, ARM64Instr_LdSt32(True/*isLoad*/, dst, am));
1740 HReg src = iselIntExpr_R(env, arg);
1741 HReg dst = widen_z_32_to_64(env, src);
1750 HReg dst = newVRegI(env);
1752 = iselIntExpr_AMode(env, arg->Iex.Load.addr, Ity_I8);
1753 addInstr(env, ARM64Instr_LdSt8(True/*isLoad*/, dst, am));
1757 HReg src = iselIntExpr_R(env, arg);
1758 HReg dst = widen_z_8_to_64(env, src);
1763 iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
1768 HReg src = iselIntExpr_R(env, arg);
1769 HReg dst = widen_s_8_to_64(env, src);
1774 HReg src = iselIntExpr_R(env, arg);
1775 HReg dst = widen_s_16_to_64(env, src);
1780 HReg src = iselIntExpr_R(env, arg);
1781 HReg dst = widen_s_32_to_64(env, src);
1786 HReg dst = newVRegI(env);
1787 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1788 addInstr(env, ARM64Instr_Unary(dst, src, ARM64un_NOT));
1792 HReg dst = newVRegI(env);
1793 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1794 addInstr(env, ARM64Instr_Unary(dst, src, ARM64un_CLZ));
1802 HReg dst = newVRegI(env);
1803 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1804 addInstr(env, ARM64Instr_Unary(dst, src, ARM64un_NEG));
1805 addInstr(env
1812 HReg dst = newVRegI(env);
1813 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1814 addInstr(env, ARM64Instr_Unary(dst, src, ARM64un_NEG));
1815 addInstr(env, ARM64Instr_Logic(dst, dst, ARM64RIL_R(src),
1817 addInstr(env, ARM64Instr_Shift(dst, dst, ARM64RI6_I6(63),
1824 HReg dst = newVRegI(env);
1825 HReg pre = iselIntExpr_R(env, e->Iex.Unop.arg);
1826 HReg src = widen_z_32_to_64(env, pre);
1827 addInstr(env, ARM64Instr_Unary(dst, src, ARM64un_NEG));
1828 addInstr(env, ARM64Instr_Logic(dst, dst, ARM64RIL_R(src),
1830 addInstr(env, ARM64Instr_Shift(dst, dst, ARM64RI6_I6(63),
1835 HReg dst = newVRegI(env);
1836 HReg src = iselV128Expr(env, e->Iex.Unop.arg);
1838 addInstr(env, ARM64Instr_VXfromQ(dst, src, laneNo));
1842 HReg dst = newVRegI(env);
1843 HReg src = iselDblExpr(env, e->Iex.Unop.arg);
1844 addInstr(env, ARM64Instr_VXfromDorS(dst, src, True/*fromD*/));
1848 HReg dst = newVRegI(env);
1849 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
1850 addInstr(env, ARM64Instr_VXfromDorS(dst, src, False/*!fromD*/));
1858 HReg zero = newVRegI(env);
1859 HReg one = newVRegI(env);
1860 HReg dst = newVRegI(env);
1861 addInstr(env, ARM64Instr_Imm64(zero, 0));
1862 addInstr(env, ARM64Instr_Imm64(one, 1));
1863 ARM64CondCode cc = iselCondCode(env, e->Iex.Unop.arg);
1864 addInstr(env, ARM64Instr_CSel(dst, one, zero, cc));
1865 addInstr(env, ARM64Instr_Shift(dst, dst, ARM64RI6_I6(63),
1867 addInstr(env, ARM64Instr_Shift(dst, dst, ARM64RI6_I6(63),
1884 HReg src = iselV128Expr(env, e->Iex.Unop.arg);
1885 HReg tmp = newVRegV(env);
1886 HReg dst = newVRegI(env);
1917 addInstr(env, ARM64Instr_VNarrowV(op, dszBlg2, tmp, src));
1918 addInstr(env, ARM64Instr_VXfromQ(dst, tmp, 0/*laneNo*/));
1923 HReg dst = newVRegI(env);
1926 HReg src = lookupIRTemp(env, e->Iex.Unop.arg->Iex.RdTmp.tmp);
1928 addInstr(env, ARM64Instr_Logic(dst, src, one, ARM64lo_AND));
1931 HReg zero = newVRegI(env);
1932 HReg one = newVRegI(env);
1933 addInstr(env, ARM64Instr_Imm64(zero, 0));
1934 addInstr(env, ARM64Instr_Imm64(one, 1));
1935 ARM64CondCode cc = iselCondCode(env, e->Iex.Unop.arg);
1936 addInstr(env, ARM64Instr_CSel(dst, one, zero, cc));
1944 return iselIntExpr_R(env, e->Iex.Unop.arg);
1957 HReg dst = newVRegI(env);
1960 addInstr(env, ARM64Instr_LdSt64(True/*isLoad*/, dst, am));
1965 HReg dst = newVRegI(env);
1968 addInstr(env, ARM64Instr_LdSt32(True/*isLoad*/, dst, am));
1973 HReg dst = newVRegI(env);
1976 addInstr(env, ARM64Instr_LdSt16(True/*isLoad*/, dst, am));
1981 HReg dst = newVRegI(env);
1984 addInstr(env, ARM64Instr_LdSt8(True/*isLoad*/, dst, am));
1992 HReg dst = newVRegI(env);
2004 Bool ok = doHelperCall( &addToSp, &rloc, env, NULL/*guard*/,
2012 addInstr(env, ARM64Instr_MovI(dst, hregARM64_X0()));
2022 HReg dst = newVRegI(env);
2030 addInstr(env, ARM64Instr_Imm64(dst, u));
2039 HReg r1 = iselIntExpr_R(env, e->Iex.ITE.iftrue);
2040 HReg r0 = iselIntExpr_R(env, e->Iex.ITE.iffalse);
2041 HReg dst = newVRegI(env);
2042 cc = iselCondCode(env, e->Iex.ITE.cond);
2043 addInstr(env, ARM64Instr_CSel(dst, r1, r0, cc));
2070 ISelEnv* env, IRExpr* e )
2072 iselInt128Expr_wrk(rHi, rLo, env, e);
2084 ISelEnv* env, IRExpr* e )
2087 vassert(typeOfIRExpr(env->type_env,e) == Ity_I128);
2096 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
2097 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
2098 HReg dstLo = newVRegI(env);
2099 HReg dstHi = newVRegI(env);
2100 addInstr(env, ARM64Instr_Mul(dstLo, argL, argR,
2102 addInstr(env, ARM64Instr_Mul(dstHi, argL, argR,
2110 *rHi = iselIntExpr_R(env, e->Iex.Binop.arg1);
2111 *rLo = iselIntExpr_R(env, e->Iex.Binop.arg2);
2127 static HReg iselV128Expr ( ISelEnv* env, IRExpr* e )
2129 HReg r = iselV128Expr_wrk( env, e );
2136 static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e )
2138 IRType ty = typeOfIRExpr(env->type_env, e);
2143 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
2150 HReg res = newVRegV(env);
2153 addInstr(env, ARM64Instr_VImmQ(res, con));
2156 addInstr(env, ARM64Instr_VImmQ(res, 0x000F));
2157 addInstr(env, ARM64Instr_VExtV(res, res, res, 12));
2160 addInstr(env, ARM64Instr_VImmQ(res, 0x000F));
2161 addInstr(env, ARM64Instr_VExtV(res, res, res, 8));
2164 addInstr(env, ARM64Instr_VImmQ(res, 0x00FF));
2165 addInstr(env, ARM64Instr_VExtV(res, res, res, 12));
2168 addInstr(env, ARM64Instr_VImmQ(res, 0x000F));
2169 addInstr(env, ARM64Instr_VExtV(res, res, res, 4));
2170 addInstr(env, ARM64Instr_VUnaryV(ARM64vecu_NOT, res, res));
2173 addInstr(env, ARM64Instr_VImmQ(res, 0x000F));
2174 addInstr(env, ARM64Instr_VExtV(res, res, res, 4));
2177 addInstr(env, ARM64Instr_VImmQ(res, 0x00FF));
2178 addInstr(env, ARM64Instr_VExtV(res, res, res, 8));
2188 HReg res = newVRegV(env);
2189 HReg rN = iselIntExpr_R(env, e->Iex.Load.addr);
2191 addInstr(env, ARM64Instr_VLdStQ(True/*isLoad*/, res, rN));
2198 HReg addr = mk_baseblock_128bit_access_addr(env, offs);
2199 HReg res = newVRegV(env);
2201 addInstr(env, ARM64Instr_VLdStQ(True/*isLoad*/, res, addr));
2219 HReg src = iselV128Expr(env, e->Iex.Unop.arg);
2220 HReg imm = newVRegV(env);
2221 HReg res = newVRegV(env);
2222 addInstr(env, ARM64Instr_VImmQ(imm, imm16));
2223 addInstr(env, ARM64Instr_VBinV(ARM64vecb_AND, res, src, imm));
2247 HReg res = newVRegV(env);
2248 HReg arg = iselV128Expr(env, e->Iex.Unop.arg);
2291 set_FPCR_rounding_mode(env, IRExpr_Const(
2294 addInstr(env, ARM64Instr_VUnaryV(op, res, arg));
2301 HReg arg = iselV128Expr(env, e->Iex.Unop.arg);
2302 HReg zero = newVRegV(env);
2303 HReg res = newVRegV(env);
2314 addInstr(env, ARM64Instr_VImmQ(zero, 0x0000));
2315 addInstr(env, ARM64Instr_VBinV(cmp, res, arg, zero));
2316 addInstr(env, ARM64Instr_VUnaryV(ARM64vecu_NOT, res, res));
2322 iselV256Expr(&vHi, &vLo, env, e->Iex.Unop.arg);
2326 HReg res = newVRegV(env);
2327 HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg);
2328 addInstr(env, ARM64Instr_VQfromX(res, arg));
2332 HReg res = newVRegV(env);
2333 HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg);
2334 addInstr(env, ARM64Instr_VQfromX(res, arg));
2335 addInstr(env, ARM64Instr_VBinV(ARM64vecb_ZIP18x16, res, res, res));
2336 addInstr(env, ARM64Instr_VShiftImmV(ARM64vecshi_SSHR16x8,
2341 HReg res = newVRegV(env);
2342 HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg);
2343 addInstr(env, ARM64Instr_VQfromX(res, arg));
2344 addInstr(env, ARM64Instr_VBinV(ARM64vecb_ZIP116x8, res, res, res));
2345 addInstr(env, ARM64Instr_VShiftImmV(ARM64vecshi_SSHR32x4,
2350 HReg res = newVRegV(env);
2351 HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg);
2352 addInstr(env, ARM64Instr_VQfromX(res, arg));
2353 addInstr(env, ARM64Instr_VBinV(ARM64vecb_ZIP132x4, res, res, res));
2354 addInstr(env, ARM64Instr_VShiftImmV(ARM64vecshi_SSHR64x2,
2368 HReg arg = iselV128Expr(env, e->Iex.Binop.arg2);
2369 HReg res = newVRegV(env);
2370 set_FPCR_rounding_mode(env, e->Iex.Binop.arg1);
2374 addInstr(env, ARM64Instr_VUnaryV(op, res, arg));
2378 HReg res = newVRegV(env);
2379 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
2380 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
2381 addInstr(env, ARM64Instr_VQfromXX(res, argL, argR));
2439 HReg res = newVRegV(env);
2440 HReg argL = iselV128Expr(env, e->Iex.Binop.arg1);
2441 HReg argR = iselV128Expr(env, e->Iex.Binop.arg2);
2574 set_FPCR_rounding_mode(env, IRExpr_Const(
2578 addInstr(env, ARM64Instr_VBinV(op, res, argR, argL));
2580 addInstr(env, ARM64Instr_VBinV(op, res, argL, argR));
2591 HReg res = newVRegV(env);
2592 HReg argL = iselV128Expr(env, e->Iex.Binop.arg1);
2593 HReg argR = iselV128Expr(env, e->Iex.Binop.arg2);
2613 addInstr(env, ARM64Instr_VMov(16, res, argR));
2614 addInstr(env, ARM64Instr_VModifyV(op, res, argL));
2698 HReg src = iselV128Expr(env, argL);
2699 HReg dst = newVRegV(env);
2700 addInstr(env, ARM64Instr_VShiftImmV(op, dst, src, amt));
2710 return iselV128Expr(env, argL);
2801 HReg src = iselV128Expr(env, argL);
2802 HReg dst = newVRegV(env);
2803 HReg fpsr = newVRegI(env);
2808 addInstr(env, ARM64Instr_Imm64(fpsr, 0));
2809 addInstr(env, ARM64Instr_FPSR(True/*toFPSR*/, fpsr));
2810 addInstr(env, ARM64Instr_VShiftImmV(op, dst, src, amt));
2811 addInstr(env, ARM64Instr_FPSR(False/*!toFPSR*/, fpsr));
2812 addInstr(env, ARM64Instr_Shift(fpsr, fpsr, ARM64RI6_I6(27),
2816 addInstr(env, ARM64Instr_Logic(fpsr,
2823 HReg scratch = newVRegV(env);
2824 addInstr(env, ARM64Instr_VQfromX(scratch, fpsr));
2825 addInstr(env, ARM64Instr_VBinV(ARM64vecb_UZP164x2,
2859 HReg src = iselV128Expr(env, argL);
2860 HReg srcZ = newVRegV(env);
2861 addInstr(env, ARM64Instr_VImmQ(srcZ, 0x0000));
2864 HReg dst = newVRegV(env);
2866 addInstr(env, ARM64Instr_VExtV(dst, src/*lo*/, srcZ/*hi*/,
2869 addInstr(env, ARM64Instr_VExtV(dst, srcZ/*lo*/, src/*hi*/,
2889 HReg iSrcL = iselIntExpr_R(env, e->Iex.Binop.arg1);
2890 HReg iSrcR = iselIntExpr_R(env, e->Iex.Binop.arg2);
2891 HReg vSrcL = newVRegV(env);
2892 HReg vSrcR = newVRegV(env);
2893 HReg dst = newVRegV(env);
2907 addInstr(env, ARM64Instr_VQfromXX(vSrcL, iSrcL, iSrcL));
2908 addInstr(env, ARM64Instr_VQfromXX(vSrcR, iSrcR, iSrcR));
2909 addInstr(env, ARM64Instr_VBinV(op, dst, vSrcL, vSrcR));
2934 HReg argL = iselV128Expr(env, triop->arg2);
2935 HReg argR = iselV128Expr(env, triop->arg3);
2936 HReg dst = newVRegV(env);
2937 set_FPCR_rounding_mode(env, triop->arg1);
2938 addInstr(env, ARM64Instr_VBinV(vecbop, dst, argL, argR));
2954 HReg srcHi = iselV128Expr(env, argHi);
2955 HReg srcLo = iselV128Expr(env, argLo);
2956 HReg dst = newVRegV(env);
2957 addInstr(env, ARM64Instr_VExtV(dst, srcLo, srcHi, amt));
2981 static HReg iselDblExpr ( ISelEnv* env, IRExpr* e )
2983 HReg r = iselDblExpr_wrk( env, e );
2993 static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e )
2995 IRType ty = typeOfIRExpr(env->type_env,e);
3000 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
3006 HReg src = newVRegI(env);
3007 HReg dst = newVRegD(env);
3008 addInstr(env, ARM64Instr_Imm64(src, con->Ico.F64i));
3009 addInstr(env, ARM64Instr_VDfromX(dst, src));
3013 HReg src = newVRegI(env);
3014 HReg dst = newVRegD(env);
3018 addInstr(env, ARM64Instr_Imm64(src, u.u64));
3019 addInstr(env, ARM64Instr_VDfromX(dst, src));
3026 HReg addr = iselIntExpr_R(env, e->Iex.Load.addr);
3027 HReg res = newVRegD(env);
3028 addInstr(env, ARM64Instr_VLdStD(True/*isLoad*/, res, addr, 0));
3035 HReg rD = newVRegD(env);
3037 addInstr(env, ARM64Instr_VLdStD(True/*isLoad*/, rD, rN, offs));
3045 HReg src = iselDblExpr(env, e->Iex.Unop.arg);
3046 HReg dst = newVRegD(env);
3047 addInstr(env, ARM64Instr_VUnaryD(ARM64fpu_NEG, dst, src));
3051 HReg src = iselDblExpr(env, e->Iex.Unop.arg);
3052 HReg dst = newVRegD(env);
3053 addInstr(env, ARM64Instr_VUnaryD(ARM64fpu_ABS, dst, src));
3057 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
3058 HReg dst = newVRegD(env);
3059 addInstr(env, ARM64Instr_VCvtSD(True/*sToD*/, dst, src));
3063 HReg src = iselF16Expr(env, e->Iex.Unop.arg);
3064 HReg dst = newVRegD(env);
3065 addInstr(env, ARM64Instr_VCvtHD(True/*hToD*/, dst, src));
3073 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
3074 HReg dst = newVRegD(env);
3077 addInstr(env, ARM64Instr_VCvtI2F(cvt_op, dst, src));
3090 HReg src = iselDblExpr(env, e->Iex.Binop.arg2);
3091 HReg dst = newVRegD(env);
3092 set_FPCR_rounding_mode(env, e->Iex.Binop.arg1);
3100 addInstr(env, ARM64Instr_VUnaryD(op, dst, src));
3107 HReg srcI = iselIntExpr_R(env, e->Iex.Binop.arg2);
3108 set_FPCR_rounding_mode(env, e->Iex.Binop.arg1);
3109 HReg dstS = newVRegD(env);
3110 addInstr(env, ARM64Instr_VCvtI2F(cvt_op, dstS, srcI));
3129 HReg argL = iselDblExpr(env, triop->arg2);
3130 HReg argR = iselDblExpr(env, triop->arg3);
3131 HReg dst = newVRegD(env);
3132 set_FPCR_rounding_mode(env, triop->arg1);
3133 addInstr(env, ARM64Instr_VBinD(dblop, dst, argL, argR));
3141 HReg r1 = iselDblExpr(env, e->Iex.ITE.iftrue);
3142 HReg r0 = iselDblExpr(env, e->Iex.ITE.iffalse);
3143 HReg dst = newVRegD(env);
3144 cc = iselCondCode(env, e->Iex.ITE.cond);
3145 addInstr(env, ARM64Instr_VFCSel(dst, r1, r0, cc, True/*64-bit*/));
3164 static HReg iselFltExpr ( ISelEnv* env, IRExpr* e )
3166 HReg r = iselFltExpr_wrk( env, e );
3176 static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e )
3178 IRType ty = typeOfIRExpr(env->type_env,e);
3183 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
3193 HReg src = newVRegI(env);
3194 HReg dst = newVRegD(env);
3195 addInstr(env, ARM64Instr_Imm64(src, 0));
3196 addInstr(env, ARM64Instr_VDfromX(dst, src));
3200 HReg src = newVRegI(env);
3201 HReg dst = newVRegD(env);
3205 addInstr(env, ARM64Instr_Imm64(src, (ULong)u.u32));
3206 addInstr(env, ARM64Instr_VDfromX(dst, src));
3213 HReg addr = iselIntExpr_R(env, e->Iex.Load.addr);
3214 HReg res = newVRegD(env);
3215 addInstr(env, ARM64Instr_VLdStS(True/*isLoad*/, res, addr, 0));
3222 HReg rD = newVRegD(env);
3224 addInstr(env, ARM64Instr_VLdStS(True/*isLoad*/, rD, rN, offs));
3232 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
3233 HReg dst = newVRegD(env);
3234 addInstr(env, ARM64Instr_VUnaryS(ARM64fpu_NEG, dst, src));
3238 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
3239 HReg dst = newVRegD(env);
3240 addInstr(env, ARM64Instr_VUnaryS(ARM64fpu_ABS, dst, src));
3244 HReg src = iselF16Expr(env, e->Iex.Unop.arg);
3245 HReg dst = newVRegD(env);
3246 addInstr(env, ARM64Instr_VCvtHS(True/*hToS*/, dst, src));
3259 HReg src = iselFltExpr(env, e->Iex.Binop.arg2);
3260 HReg dst = newVRegD(env);
3261 set_FPCR_rounding_mode(env, e->Iex.Binop.arg1);
3269 addInstr(env, ARM64Instr_VUnaryS(op, dst, src));
3273 HReg srcD = iselDblExpr(env, e->Iex.Binop.arg2);
3274 set_FPCR_rounding_mode(env, e->Iex.Binop.arg1);
3275 HReg dstS = newVRegD(env);
3276 addInstr(env, ARM64Instr_VCvtSD(False/*!sToD*/, dstS, srcD));
3291 HReg srcI = iselIntExpr_R(env, e->Iex.Binop.arg2);
3292 set_FPCR_rounding_mode(env, e->Iex.Binop.arg1);
3293 HReg dstS = newVRegD(env);
3294 addInstr(env, ARM64Instr_VCvtI2F(cvt_op, dstS, srcI));
3313 HReg argL = iselFltExpr(env, triop->arg2);
3314 HReg argR = iselFltExpr(env, triop->arg3);
3315 HReg dst = newVRegD(env);
3316 set_FPCR_rounding_mode(env, triop->arg1);
3317 addInstr(env, ARM64Instr_VBinS(sglop, dst, argL, argR));
3325 HReg r1 = iselFltExpr(env, e->Iex.ITE.iftrue);
3326 HReg r0 = iselFltExpr(env, e->Iex.ITE.iffalse);
3327 HReg dst = newVRegD(env);
3328 cc = iselCondCode(env, e->Iex.ITE.cond);
3329 addInstr(env, ARM64Instr_VFCSel(dst, r1, r0, cc, False/*!64-bit*/));
3348 static HReg iselF16Expr ( ISelEnv* env, IRExpr* e )
3350 HReg r = iselF16Expr_wrk( env, e );
3360 static HReg iselF16Expr_wrk ( ISelEnv* env, IRExpr* e )
3362 IRType ty = typeOfIRExpr(env->type_env,e);
3369 HReg rD = newVRegD(env);
3371 addInstr(env, ARM64Instr_VLdStH(True/*isLoad*/, rD, rN, offs));
3379 HReg srcS = iselFltExpr(env, e->Iex.Binop.arg2);
3380 set_FPCR_rounding_mode(env, e->Iex.Binop.arg1);
3381 HReg dstH = newVRegD(env);
3382 addInstr(env, ARM64Instr_VCvtHS(False/*!hToS*/, dstH, srcS));
3386 HReg srcD = iselDblExpr(env, e->Iex.Binop.arg2);
3387 set_FPCR_rounding_mode(env, e->Iex.Binop.arg1);
3388 HReg dstH = newVRegD(env);
3389 addInstr(env, ARM64Instr_VCvtHD(False/*!hToD*/, dstH, srcD));
3407 ISelEnv* env, IRExpr* e )
3409 iselV256Expr_wrk( rHi, rLo, env, e );
3418 ISelEnv* env, IRExpr* e )
3421 IRType ty = typeOfIRExpr(env->type_env,e);
3426 lookupIRTempPair( rHi, rLo, env, e->Iex.RdTmp.tmp);
3433 *rHi = iselV128Expr(env, e->Iex.Binop.arg1);
3434 *rLo = iselV128Expr(env, e->Iex.Binop.arg2);
3454 HReg argL = iselV128Expr(env, e->Iex.Binop.arg1);
3455 HReg argR = iselV128Expr(env, e->Iex.Binop.arg2);
3456 HReg fpsr = newVRegI(env);
3457 HReg resHi = newVRegV(env);
3458 HReg resLo = newVRegV(env);
3483 addInstr(env, ARM64Instr_Imm64(fpsr, 0));
3484 addInstr(env, ARM64Instr_FPSR(True/*toFPSR*/, fpsr));
3485 addInstr(env, ARM64Instr_VBinV(op, resLo, argL, argR));
3486 addInstr(env, ARM64Instr_FPSR(False/*!toFPSR*/, fpsr));
3487 addInstr(env, ARM64Instr_Shift(fpsr, fpsr, ARM64RI6_I6(27),
3491 addInstr(env, ARM64Instr_Logic(fpsr, fpsr, ril_one, ARM64lo_AND));
3494 addInstr(env, ARM64Instr_VQfromX(resHi, fpsr));
3515 static void iselStmt ( ISelEnv* env, IRStmt* stmt )
3527 IRType tya = typeOfIRExpr(env->type_env, stmt->Ist.Store.addr);
3528 IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data);
3535 HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data);
3536 ARM64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr, tyd);
3537 addInstr(env, ARM64Instr_LdSt64(False/*!isLoad*/, rD, am));
3541 HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data);
3542 ARM64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr, tyd);
3543 addInstr(env, ARM64Instr_LdSt32(False/*!isLoad*/, rD, am));
3547 HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data);
3548 ARM64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr, tyd);
3549 addInstr(env, ARM64Instr_LdSt16(False/*!isLoad*/, rD, am));
3553 HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data);
3554 ARM64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr, tyd);
3555 addInstr(env, ARM64Instr_LdSt8(False/*!isLoad*/, rD, am));
3559 HReg qD = iselV128Expr(env, stmt->Ist.Store.data);
3560 HReg addr = iselIntExpr_R(env, stmt->Ist.Store.addr);
3561 addInstr(env, ARM64Instr_VLdStQ(False/*!isLoad*/, qD, addr));
3565 HReg dD = iselDblExpr(env, stmt->Ist.Store.data);
3566 HReg addr = iselIntExpr_R(env, stmt->Ist.Store.addr);
3567 addInstr(env, ARM64Instr_VLdStD(False/*!isLoad*/, dD, addr, 0));
3571 HReg sD = iselFltExpr(env, stmt->Ist.Store.data);
3572 HReg addr = iselIntExpr_R(env, stmt->Ist.Store.addr);
3573 addInstr(env, ARM64Instr_VLdStS(False/*!isLoad*/, sD, addr, 0));
3582 IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Put.data);
3585 HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data);
3587 addInstr(env, ARM64Instr_LdSt64(False/*!isLoad*/, rD, am));
3591 HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data);
3593 addInstr(env, ARM64Instr_LdSt32(False/*!isLoad*/, rD, am));
3597 HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data);
3599 addInstr(env, ARM64Instr_LdSt16(False/*!isLoad*/, rD, am));
3603 HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data);
3605 addInstr(env, ARM64Instr_LdSt8(False/*!isLoad*/, rD, am));
3609 HReg qD = iselV128Expr(env, stmt->Ist.Put.data);
3610 HReg addr = mk_baseblock_128bit_access_addr(env, offs);
3611 addInstr(env, ARM64Instr_VLdStQ(False/*!isLoad*/, qD, addr));
3615 HReg dD = iselDblExpr(env, stmt->Ist.Put.data);
3617 addInstr(env, ARM64Instr_VLdStD(False/*!isLoad*/, dD, bbp, offs));
3621 HReg sD = iselFltExpr(env, stmt->Ist.Put.data);
3623 addInstr(env, ARM64Instr_VLdStS(False/*!isLoad*/, sD, bbp, offs));
3627 HReg hD = iselF16Expr(env, stmt->Ist.Put.data);
3629 addInstr(env, ARM64Instr_VLdStH(False/*!isLoad*/, hD, bbp, offs));
3640 IRType ty = typeOfIRTemp(env->type_env, tmp);
3644 HReg dst = lookupIRTemp(env, tmp);
3645 HReg rD = iselIntExpr_R(env, stmt->Ist.WrTmp.data);
3646 addInstr(env, ARM64Instr_MovI(dst, rD));
3660 HReg zero = newVRegI(env);
3661 HReg one = newVRegI(env);
3662 HReg dst = lookupIRTemp(env, tmp);
3663 addInstr(env, ARM64Instr_Imm64(zero, 0));
3664 addInstr(env, ARM64Instr_Imm64(one, 1));
3665 ARM64CondCode cc = iselCondCode(env, stmt->Ist.WrTmp.data);
3666 addInstr(env, ARM64Instr_CSel(dst, one, zero, cc));
3670 HReg src = iselDblExpr(env, stmt->Ist.WrTmp.data);
3671 HReg dst = lookupIRTemp(env, tmp);
3672 addInstr(env, ARM64Instr_VMov(8, dst, src));
3676 HReg src = iselFltExpr(env, stmt->Ist.WrTmp.data);
3677 HReg dst = lookupIRTemp(env, tmp);
3678 addInstr(env, ARM64Instr_VMov(8/*yes, really*/, dst, src));
3682 HReg src = iselV128Expr(env, stmt->Ist.WrTmp.data);
3683 HReg dst = lookupIRTemp(env, tmp);
3684 addInstr(env, ARM64Instr_VMov(16, dst, src));
3689 iselV256Expr(&srcHi,&srcLo, env, stmt->Ist.WrTmp.data);
3690 lookupIRTempPair( &dstHi, &dstLo, env, tmp);
3691 addInstr(env, ARM64Instr_VMov(16, dstHi, srcHi));
3692 addInstr(env, ARM64Instr_VMov(16, dstLo, srcLo));
3706 retty = typeOfIRTemp(env->type_env, d->tmp);
3725 doHelperCall( &addToSp, &rloc, env, d->guard, d->cee, retty, d->args );
3742 HReg dst = lookupIRTemp(env, d->tmp);
3743 addInstr(env, ARM64Instr_MovI(dst, hregARM64_X0()) );
3755 HReg dst = lookupIRTemp(env, d->tmp);
3756 HReg tmp = newVRegI(env); // the address of the returned value
3757 addInstr(env, ARM64Instr_FromSP(tmp)); // tmp = SP
3758 addInstr(env, ARM64Instr_Arith(tmp, tmp,
3761 addInstr(env, ARM64Instr_VLdStQ(True/*isLoad*/, dst, tmp));
3762 addInstr(env, ARM64Instr_AddToSP(addToSp));
3777 IRType ty = typeOfIRTemp(env->type_env, res);
3781 HReg r_dst = lookupIRTemp(env, res);
3782 HReg raddr = iselIntExpr_R(env, stmt->Ist.LLSC.addr);
3790 addInstr(env, ARM64Instr_MovI(hregARM64_X4(), raddr));
3791 addInstr(env, ARM64Instr_LdrEX(szB));
3792 addInstr(env, ARM64Instr_MovI(r_dst, hregARM64_X2()));
3798 IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.LLSC.storedata);
3802 HReg rD = iselIntExpr_R(env, stmt->Ist.LLSC.storedata);
3803 HReg rA = iselIntExpr_R(env, stmt->Ist.LLSC.addr);
3811 addInstr(env, ARM64Instr_MovI(hregARM64_X2(), rD));
3812 addInstr(env, ARM64Instr_MovI(hregARM64_X4(), rA));
3813 addInstr(env, ARM64Instr_StrEX(szB));
3821 IRType ty = typeOfIRTemp(env->type_env, res);
3822 HReg r_res = lookupIRTemp(env, res);
3826 addInstr(env, ARM64Instr_Logic(r_res, hregARM64_X0(), one,
3829 addInstr(env, ARM64Instr_Logic(r_res, r_res, one,
3840 addInstr(env, ARM64Instr_MFence());
3868 = iselCondCode(env, stmt->Ist.Exit.guard);
3876 if (env->chainingAllowed) {
3881 = ((Addr64)stmt->Ist.Exit.dst->Ico.U64) > env->max_ga;
3883 addInstr(env, ARM64Instr_XDirect(stmt->Ist.Exit.dst->Ico.U64,
3889 HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
3890 addInstr(env, ARM64Instr_XAssisted(r, amPC, cc, Ijk_Boring));
3911 static void iselNext ( ISelEnv* env,
3929 if (env->chainingAllowed) {
3934 = ((Addr64)cdst->Ico.U64) > env->max_ga;
3936 addInstr(env, ARM64Instr_XDirect(cdst->Ico.U64,
3943 HReg r = iselIntExpr_R(env, next);
3944 addInstr(env, ARM64Instr_XAssisted(r, amPC, ARM64cc_AL,
3954 HReg r = iselIntExpr_R(env, next);
3956 if (env->chainingAllowed) {
3957 addInstr(env, ARM64Instr_XIndir(r, amPC, ARM64cc_AL));
3959 addInstr(env, ARM64Instr_XAssisted(r, amPC, ARM64cc_AL,
3979 HReg r = iselIntExpr_R(env, next);
3981 addInstr(env, ARM64Instr_XAssisted(r, amPC, ARM64cc_AL, jk));
4015 ISelEnv* env;
4029 env = LibVEX_Alloc_inline(sizeof(ISelEnv));
4030 env->vreg_ctr = 0;
4033 env->code = newHInstrArray();
4035 /* Copy BB's type env. */
4036 env->type_env = bb->tyenv;
4040 env->n_vregmap = bb->tyenv->types_used;
4041 env->vregmap = LibVEX_Alloc_inline(env->n_vregmap * sizeof(HReg));
4042 env->vregmapHI = LibVEX_Alloc_inline(env->n_vregmap * sizeof(HReg));
4045 env->chainingAllowed = chainingAllowed;
4046 env->hwcaps = hwcaps_host;
4047 env->previous_rm = NULL;
4048 env->max_ga = max_ga;
4053 for (i = 0; i < env->n_vregmap; i++) {
4080 env->vregmap[i] = hreg;
4081 env->vregmapHI[i] = hregHI;
4083 env->vreg_ctr = j;
4088 addInstr(env, ARM64Instr_EvCheck(amCounter, amFailAddr));
4095 addInstr(env, ARM64Instr_ProfInc());
4100 iselStmt(env, bb->stmts[i]);
4102 iselNext(env, bb->next, bb->jumpkind, bb->offsIP);
4105 env->code->n_vregs = env->vreg_ctr;
4106 return env->code;
