Lines Matching defs:env
129 static HReg lookupIRTemp ( ISelEnv* env, IRTemp tmp )
132 vassert(tmp < env->n_vregmap);
133 return env->vregmap[tmp];
136 static void lookupIRTemp64 ( HReg* vrHI, HReg* vrLO, ISelEnv* env, IRTemp tmp )
139 vassert(tmp < env->n_vregmap);
140 vassert(! hregIsInvalid(env->vregmapHI[tmp]));
141 *vrLO = env->vregmap[tmp];
142 *vrHI = env->vregmapHI[tmp];
145 static void addInstr ( ISelEnv* env, ARMInstr* instr )
147 addHInstr(env->code, instr);
154 static HReg newVRegI ( ISelEnv* env )
156 HReg reg = mkHReg(True/*virtual reg*/, HRcInt32, 0/*enc*/, env->vreg_ctr);
157 env->vreg_ctr++;
161 static HReg newVRegD ( ISelEnv* env )
163 HReg reg = mkHReg(True/*virtual reg*/, HRcFlt64, 0/*enc*/, env->vreg_ctr);
164 env->vreg_ctr++;
168 static HReg newVRegF ( ISelEnv* env )
170 HReg reg = mkHReg(True/*virtual reg*/, HRcFlt32, 0/*enc*/, env->vreg_ctr);
171 env->vreg_ctr++;
175 static HReg newVRegV ( ISelEnv* env )
177 HReg reg = mkHReg(True/*virtual reg*/, HRcVec128, 0/*enc*/, env->vreg_ctr);
178 env->vreg_ctr++;
209 static ARMAMode1* iselIntExpr_AMode1_wrk ( ISelEnv* env, IRExpr* e );
210 static ARMAMode1* iselIntExpr_AMode1 ( ISelEnv* env, IRExpr* e );
212 static ARMAMode2* iselIntExpr_AMode2_wrk ( ISelEnv* env, IRExpr* e );
213 static ARMAMode2* iselIntExpr_AMode2 ( ISelEnv* env, IRExpr* e );
215 static ARMAModeV* iselIntExpr_AModeV_wrk ( ISelEnv* env, IRExpr* e );
216 static ARMAModeV* iselIntExpr_AModeV ( ISelEnv* env, IRExpr* e );
218 static ARMAModeN* iselIntExpr_AModeN_wrk ( ISelEnv* env, IRExpr* e );
219 static ARMAModeN* iselIntExpr_AModeN ( ISelEnv* env, IRExpr* e );
222 ( /*OUT*/Bool* didInv, Bool mayInv, ISelEnv* env, IRExpr* e );
224 ( /*OUT*/Bool* didInv, Bool mayInv, ISelEnv* env, IRExpr* e );
226 static ARMRI5* iselIntExpr_RI5_wrk ( ISelEnv* env, IRExpr* e );
227 static ARMRI5* iselIntExpr_RI5 ( ISelEnv* env, IRExpr* e );
229 static ARMCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e );
230 static ARMCondCode iselCondCode ( ISelEnv* env, IRExpr* e );
232 static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e );
233 static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e );
236 ISelEnv* env, IRExpr* e );
238 ISelEnv* env, IRExpr* e );
240 static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e );
241 static HReg iselDblExpr ( ISelEnv* env, IRExpr* e );
243 static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e );
244 static HReg iselFltExpr ( ISelEnv* env, IRExpr* e );
246 static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e );
247 static HReg iselNeon64Expr ( ISelEnv* env, IRExpr* e );
249 static HReg iselNeonExpr_wrk ( ISelEnv* env, IRExpr* e );
250 static HReg iselNeonExpr ( ISelEnv* env, IRExpr* e );
290 static void set_VFP_rounding_default ( ISelEnv* env )
295 HReg rTmp = newVRegI(env);
296 addInstr(env, ARMInstr_Imm32(rTmp, DEFAULT_FPSCR));
297 addInstr(env, ARMInstr_FPSCR(True/*toFPSCR*/, rTmp));
306 void set_VFP_rounding_mode ( ISelEnv* env, IRExpr* mode )
322 HReg irrm = iselIntExpr_R(env, mode);
323 HReg tL = newVRegI(env);
324 HReg tR = newVRegI(env);
325 HReg t3 = newVRegI(env);
334 addInstr(env, ARMInstr_Shift(ARMsh_SHL, tL, irrm, ARMRI5_I5(1)));
335 addInstr(env, ARMInstr_Shift(ARMsh_SHR, tR, irrm, ARMRI5_I5(1)));
336 addInstr(env, ARMInstr_Alu(ARMalu_AND, tL, tL, ARMRI84_I84(2,0)));
337 addInstr(env, ARMInstr_Alu(ARMalu_AND, tR, tR, ARMRI84_I84(1,0)));
338 addInstr(env, ARMInstr_Alu(ARMalu_OR, t3, tL, ARMRI84_R(tR)));
339 addInstr(env, ARMInstr_Shift(ARMsh_SHL, t3, t3, ARMRI5_I5(22)));
340 addInstr(env, ARMInstr_FPSCR(True/*toFPSCR*/, t3));
382 ISelEnv* env,
526 aTy = typeOfIRExpr(env->type_env, arg);
532 addInstr(env, mk_iMOVds_RR( argregs[nextArgReg],
533 iselIntExpr_R(env, arg) ));
544 addInstr(env, ARMInstr_Imm32( argregs[nextArgReg], 0xAA ));
550 iselInt64Expr(&raHi, &raLo, env, arg);
551 addInstr(env, mk_iMOVds_RR( argregs[nextArgReg], raLo ));
553 addInstr(env, mk_iMOVds_RR( argregs[nextArgReg], raHi ));
558 addInstr(env, mk_iMOVds_RR( argregs[nextArgReg],
583 aTy = typeOfIRExpr(env->type_env, arg);
589 tmpregs[nextArgReg] = iselIntExpr_R(env, args[i]);
599 iselInt64Expr(&raHi, &raLo, env, args[i]);
629 cc = iselCondCode( env, guard );
636 addInstr(env, ARMInstr_Imm32( argregs[i], 0xAA ));
641 addInstr( env, mk_iMOVds_RR( argregs[i], tmpregs[i] ) );
704 addInstr(env, ARMInstr_Call( cc, target, nextArgReg, *retloc ));
758 static ARMAMode1* iselIntExpr_AMode1 ( ISelEnv* env, IRExpr* e )
760 ARMAMode1* am = iselIntExpr_AMode1_wrk(env, e);
765 static ARMAMode1* iselIntExpr_AMode1_wrk ( ISelEnv* env, IRExpr* e )
767 IRType ty = typeOfIRExpr(env->type_env,e);
782 reg = iselIntExpr_R(env, e->Iex.Binop.arg1);
790 HReg reg = iselIntExpr_R(env, e);
824 static ARMAMode2* iselIntExpr_AMode2 ( ISelEnv* env, IRExpr* e )
826 ARMAMode2* am = iselIntExpr_AMode2_wrk(env, e);
831 static ARMAMode2* iselIntExpr_AMode2_wrk ( ISelEnv* env, IRExpr* e )
833 IRType ty = typeOfIRExpr(env->type_env,e);
848 reg = iselIntExpr_R(env, e->Iex.Binop.arg1);
856 HReg reg = iselIntExpr_R(env, e);
878 static ARMAModeV* iselIntExpr_AModeV ( ISelEnv* env, IRExpr* e )
880 ARMAModeV* am = iselIntExpr_AModeV_wrk(env, e);
885 static ARMAModeV* iselIntExpr_AModeV_wrk ( ISelEnv* env, IRExpr* e )
887 IRType ty = typeOfIRExpr(env->type_env,e);
900 reg = iselIntExpr_R(env, e->Iex.Binop.arg1);
908 HReg reg = iselIntExpr_R(env, e);
916 static ARMAModeN* iselIntExpr_AModeN ( ISelEnv* env, IRExpr* e )
918 return iselIntExpr_AModeN_wrk(env, e);
921 static ARMAModeN* iselIntExpr_AModeN_wrk ( ISelEnv* env, IRExpr* e )
923 HReg reg = iselIntExpr_R(env, e);
938 ISelEnv* env, IRExpr* e )
943 ri = iselIntExpr_RI84_wrk(didInv, mayInv, env, e);
959 env, IRExpr* e )
961 IRType ty = typeOfIRExpr(env->type_env,e);
988 HReg r = iselIntExpr_R ( env, e );
998 static ARMRI5* iselIntExpr_RI5 ( ISelEnv* env, IRExpr* e )
1000 ARMRI5* ri = iselIntExpr_RI5_wrk(env, e);
1015 static ARMRI5* iselIntExpr_RI5_wrk ( ISelEnv* env, IRExpr* e )
1017 IRType ty = typeOfIRExpr(env->type_env,e);
1037 HReg r = iselIntExpr_R ( env, e );
1049 static ARMCondCode iselCondCode ( ISelEnv* env, IRExpr* e )
1051 ARMCondCode cc = iselCondCode_wrk(env,e);
1056 static ARMCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e )
1059 vassert(typeOfIRExpr(env->type_env,e) == Ity_I1);
1063 HReg rTmp = lookupIRTemp(env, e->Iex.RdTmp.tmp);
1066 addInstr(env, ARMInstr_CmpOrTst(False/*test*/, rTmp, one));
1073 return 1 ^ iselCondCode(env, e->Iex.Unop.arg);
1080 HReg rTmp = iselIntExpr_R(env, e->Iex.Unop.arg);
1082 addInstr(env, ARMInstr_CmpOrTst(False/*test*/, rTmp, one));
1090 HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg);
1092 addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r1, xFF));
1100 HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg);
1102 addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, r1, zero));
1111 HReg tmp = newVRegI(env);
1113 iselInt64Expr(&tHi, &tLo, env, e->Iex.Unop.arg);
1114 addInstr(env, ARMInstr_Alu(ARMalu_OR, tmp, tHi, ARMRI84_R(tLo)));
1115 addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, tmp, zero));
1127 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1129 env, e->Iex.Binop.arg2);
1130 addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, argL, argR));
1149 r = newVRegI(env);
1150 addInstr(env, ARMInstr_Imm32(r, 0));
1151 addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, r, ARMRI84_R(r)));
1173 static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e )
1175 HReg r = iselIntExpr_R_wrk(env, e);
1186 static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
1188 IRType ty = typeOfIRExpr(env->type_env,e);
1195 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
1200 HReg dst = newVRegI(env);
1206 ARMAMode1* amode = iselIntExpr_AMode1 ( env, e->Iex.Load.addr );
1207 addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, dst, amode));
1211 ARMAMode2* amode = iselIntExpr_AMode2 ( env, e->Iex.Load.addr );
1212 addInstr(env, ARMInstr_LdSt16(ARMcc_AL,
1218 ARMAMode1* amode = iselIntExpr_AMode1 ( env, e->Iex.Load.addr );
1219 addInstr(env, ARMInstr_LdSt8U(ARMcc_AL, True/*isLoad*/, dst, amode));
1232 //zz HReg junk = newVRegF(env);
1233 //zz HReg dst = newVRegI(env);
1234 //zz HReg srcL = iselDblExpr(env, triop->arg2);
1235 //zz HReg srcR = iselDblExpr(env, triop->arg3);
1238 //zz addInstr(env, X86Instr_FpBinary(
1245 //zz addInstr(env, X86Instr_FpStSW_AX());
1246 //zz addInstr(env, mk_iMOVsd_RR(hregX86_EAX(), dst));
1247 //zz addInstr(env, X86Instr_Alu32R(Xalu_AND, X86RMI_Imm(0x4700), dst));
1264 HReg dst = newVRegI(env);
1265 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1267 env, e->Iex.Binop.arg2);
1268 addInstr(env, ARMInstr_Alu(didInv ? ARMalu_BIC : ARMalu_AND,
1277 HReg dst = newVRegI(env);
1278 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1280 env, e->Iex.Binop.arg2);
1281 addInstr(env, ARMInstr_Alu(aop, dst, argL, argR));
1293 HReg dst = newVRegI(env);
1294 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1295 ARMRI5* argR = iselIntExpr_RI5(env, e->Iex.Binop.arg2);
1296 addInstr(env, ARMInstr_Shift(sop, dst, argL, argR));
1305 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1306 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1307 HReg dst = newVRegI(env);
1308 addInstr(env, mk_iMOVds_RR(hregARM_R2(), argL));
1309 addInstr(env, mk_iMOVds_RR(hregARM_R3(), argR));
1310 addInstr(env, ARMInstr_Mul(ARMmul_PLAIN));
1311 addInstr(env, mk_iMOVds_RR(dst, hregARM_R0()));
1318 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1319 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1320 HReg dst = newVRegI(env);
1321 addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, argL,
1323 addInstr(env, mk_iMOVds_RR(dst, argL));
1324 addInstr(env, ARMInstr_CMov(ARMcc_LO, dst, ARMRI84_R(argR)));
1329 HReg dL = iselDblExpr(env, e->Iex.Binop.arg1);
1330 HReg dR = iselDblExpr(env, e->Iex.Binop.arg2);
1331 HReg dst = newVRegI(env);
1334 addInstr(env, ARMInstr_VCmpD(dL, dR));
1336 addInstr(env, ARMInstr_Imm32(dst, 0));
1337 addInstr(env, ARMInstr_CMov(ARMcc_EQ, dst, ARMRI84_I84(0x40,0))); //EQ
1338 addInstr(env, ARMInstr_CMov(ARMcc_MI, dst, ARMRI84_I84(0x01,0))); //LT
1339 addInstr(env, ARMInstr_CMov(ARMcc_GT, dst, ARMRI84_I84(0x00,0))); //GT
1340 addInstr(env, ARMInstr_CMov(ARMcc_VS, dst, ARMRI84_I84(0x45,0))); //UN
1352 HReg valD = iselDblExpr(env, e->Iex.Binop.arg2);
1353 set_VFP_rounding_mode(env, e->Iex.Binop.arg1);
1355 HReg valF = newVRegF(env);
1356 addInstr(env, ARMInstr_VCvtID(False/*!iToD*/, syned,
1358 set_VFP_rounding_default(env);
1360 HReg dst = newVRegI(env);
1361 addInstr(env, ARMInstr_VXferS(False/*!toS*/, valF, dst));
1368 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
1369 HReg res = newVRegI(env);
1370 HReg arg = iselNeon64Expr(env, e->Iex.Binop.arg1);
1373 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
1384 addInstr(env, ARMInstr_NUnaryS(ARMneon_GETELEMS,
1394 && !(env->hwcaps & VEX_HWCAPS_ARM_NEON)) {
1402 iselInt64Expr(&rHi, &rLo, env, e->Iex.Binop.arg1);
1410 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
1411 HReg res = newVRegI(env);
1412 HReg arg = iselNeonExpr(env, e->Iex.Binop.arg1);
1415 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
1426 addInstr(env, ARMInstr_NUnaryS(ARMneon_GETELEMS,
1492 HReg regL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1493 HReg regR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1494 HReg res = newVRegI(env);
1495 addInstr(env, mk_iMOVds_RR(hregARM_R0(), regL));
1496 addInstr(env, mk_iMOVds_RR(hregARM_R1(), regR));
1497 addInstr(env, ARMInstr_Call( ARMcc_AL, (Addr)fn,
1499 addInstr(env, mk_iMOVds_RR(res, hregARM_R0()));
1516 //zz HReg dst = newVRegI(env);
1517 //zz HReg src = iselIntExpr_R(env, expr32);
1518 //zz addInstr(env, mk_iMOVsd_RR(src,dst) );
1519 //zz addInstr(env, X86Instr_Alu32R(Xalu_AND,
1532 //zz HReg dst = newVRegI(env);
1533 //zz X86AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] );
1534 //zz addInstr(env, X86Instr_LoadEX(1,False,amode,dst));
1546 //zz HReg dst = newVRegI(env);
1547 //zz X86AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] );
1548 //zz addInstr(env, X86Instr_LoadEX(1,True,amode,dst));
1560 //zz HReg dst = newVRegI(env);
1561 //zz X86AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] );
1562 //zz addInstr(env, X86Instr_LoadEX(2,False,amode,dst));
1573 //zz dst = newVRegI(env);
1576 //zz addInstr(env, X86Instr_LoadEX(1,False,amode,dst));
1587 //zz dst = newVRegI(env);
1590 //zz addInstr(env, X86Instr_LoadEX(2,False,amode,dst));
1597 HReg dst = newVRegI(env);
1598 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1599 addInstr(env, ARMInstr_Alu(ARMalu_AND,
1606 //zz HReg dst = newVRegI(env);
1607 //zz HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1609 //zz addInstr(env, mk_iMOVsd_RR(src,dst) );
1610 //zz addInstr(env, X86Instr_Alu32R(Xalu_AND,
1617 HReg dst = newVRegI(env);
1618 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1620 addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, src, amt));
1621 addInstr(env, ARMInstr_Shift(ARMsh_SHR, dst, dst, amt));
1626 HReg dst = newVRegI(env);
1627 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1629 addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, src, amt));
1630 addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, amt));
1636 HReg dst = newVRegI(env);
1637 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1638 addInstr(env, ARMInstr_Unary(ARMun_NOT, dst, src));
1643 iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
1648 iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
1653 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
1654 HReg tHi = newVRegI(env);
1655 HReg tLo = newVRegI(env);
1656 HReg tmp = iselNeon64Expr(env, e->Iex.Unop.arg);
1657 addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo));
1661 iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
1672 HReg dst = lookupIRTemp(env, e->Iex.Unop.arg->Iex.RdTmp.tmp);
1677 HReg dst = newVRegI(env);
1678 ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg);
1679 addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0)));
1680 addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0)));
1685 HReg dst = newVRegI(env);
1686 ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg);
1691 addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0)));
1692 addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0)));
1693 addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, dst, amt));
1694 addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, amt));
1703 //zz HReg dst = newVRegI(env);
1704 //zz X86CondCode cond = iselCondCode(env, e->Iex.Unop.arg);
1705 //zz addInstr(env, X86Instr_Set32(cond,dst));
1706 //zz addInstr(env, X86Instr_Sh32(Xsh_SHL, 31, dst));
1707 //zz addInstr(env, X86Instr_Sh32(Xsh_SAR, 31, dst));
1712 //zz HReg dst = newVRegI(env);
1713 //zz HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1714 //zz addInstr(env, X86Instr_Bsfr32(True,src,dst));
1719 HReg dst = newVRegI(env);
1720 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1721 addInstr(env, ARMInstr_Unary(ARMun_CLZ, dst, src));
1726 HReg dst = newVRegI(env);
1727 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1728 addInstr(env, ARMInstr_Unary(ARMun_NEG, dst, src));
1729 addInstr(env, ARMInstr_Alu(ARMalu_OR, dst, dst, ARMRI84_R(src)));
1730 addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, ARMRI5_I5(31)));
1735 HReg dst = newVRegI(env);
1736 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1737 addInstr(env, ARMInstr_Unary(ARMun_NEG, dst, src));
1738 addInstr(env, ARMInstr_Alu(ARMalu_OR, dst, dst, ARMRI84_R(src)));
1743 //zz HReg dst = newVRegI(env);
1744 //zz HReg vec = iselVecExpr(env, e->Iex.Unop.arg);
1746 //zz sub_from_esp(env, 16);
1747 //zz addInstr(env, X86Instr_SseLdSt(False/*store*/, vec, esp0));
1748 //zz addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(esp0), dst ));
1749 //zz add_to_esp(env, 16);
1754 HReg dst = newVRegI(env);
1755 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
1756 addInstr(env, ARMInstr_VXferS(False/*!toS*/, src, dst));
1765 return iselIntExpr_R(env, e->Iex.Unop.arg);
1783 HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg);
1784 HReg res = newVRegI(env);
1785 addInstr(env, mk_iMOVds_RR(hregARM_R0(), arg));
1786 addInstr(env, ARMInstr_Call( ARMcc_AL, (Addr)fn,
1788 addInstr(env, mk_iMOVds_RR(res, hregARM_R0()));
1800 HReg dst = newVRegI(env);
1801 addInstr(env, ARMInstr_LdSt32(
1808 //zz HReg dst = newVRegI(env);
1809 //zz addInstr(env, X86Instr_LoadEX(
1822 //zz env, e->Iex.GetI.descr,
1824 //zz HReg dst = newVRegI(env);
1826 //zz addInstr(env, X86Instr_LoadEX( 1, False, am, dst ));
1830 //zz addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Mem(am), dst));
1838 env);
1850 Bool ok = doHelperCall( &addToSp, &rloc, env, NULL/*guard*/,
1858 addInstr(env, mk_iMOVds_RR(dst, hregARM_R0()));
1868 HReg dst = newVRegI(env);
1875 addInstr(env, ARMInstr_Imm32(dst, u));
1884 HReg r1 = iselIntExpr_R(env, e->Iex.ITE.iftrue);
1885 ARMRI84* r0 = iselIntExpr_RI84(NULL, False, env, e->Iex.ITE.iffalse);
1886 HReg dst = newVRegI(env);
1887 addInstr(env, mk_iMOVds_RR(dst, r1));
1888 cc = iselCondCode(env, e->Iex.ITE.cond);
1889 addInstr(env, ARMInstr_CMov(cc ^ 1, dst, r0));
1913 static void iselInt64Expr ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e )
1915 iselInt64Expr_wrk(rHi, rLo, env, e);
1926 static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e )
1929 vassert(typeOfIRExpr(env->type_env,e) == Ity_I64);
1936 HReg tHi = newVRegI(env);
1937 HReg tLo = newVRegI(env);
1939 addInstr(env, ARMInstr_Imm32(tHi, wHi));
1940 addInstr(env, ARMInstr_Imm32(tLo, wLo));
1948 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
1949 HReg tHi = newVRegI(env);
1950 HReg tLo = newVRegI(env);
1951 HReg tmp = iselNeon64Expr(env, e);
1952 addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo));
1956 lookupIRTemp64( rHi, rLo, env, e->Iex.RdTmp.tmp);
1965 rA = iselIntExpr_R(env, e->Iex.Load.addr);
1966 tHi = newVRegI(env);
1967 tLo = newVRegI(env);
1968 addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/,
1970 addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/,
1981 HReg tHi = newVRegI(env);
1982 HReg tLo = newVRegI(env);
1983 addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, tHi, am4));
1984 addInstr(env, ARMInstr_LdSt32(ARMcc_AL, True/*isLoad*/, tLo, am0));
1997 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1998 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1999 HReg tHi = newVRegI(env);
2000 HReg tLo = newVRegI(env);
2003 addInstr(env, mk_iMOVds_RR(hregARM_R2(), argL));
2004 addInstr(env, mk_iMOVds_RR(hregARM_R3(), argR));
2005 addInstr(env, ARMInstr_Mul(mop));
2006 addInstr(env, mk_iMOVds_RR(tHi, hregARM_R1()));
2007 addInstr(env, mk_iMOVds_RR(tLo, hregARM_R0()));
2015 HReg tHi = newVRegI(env);
2016 HReg tLo = newVRegI(env);
2017 iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
2018 iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
2019 addInstr(env, ARMInstr_Alu(ARMalu_OR, tHi, xHi, ARMRI84_R(yHi)));
2020 addInstr(env, ARMInstr_Alu(ARMalu_OR, tLo, xLo, ARMRI84_R(yLo)));
2028 HReg tHi = newVRegI(env);
2029 HReg tLo = newVRegI(env);
2030 iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
2031 iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
2032 addInstr(env, ARMInstr_Alu(ARMalu_ADDS, tLo, xLo, ARMRI84_R(yLo)));
2033 addInstr(env, ARMInstr_Alu(ARMalu_ADC, tHi, xHi, ARMRI84_R(yHi)));
2041 *rHi = iselIntExpr_R(env, e->Iex.Binop.arg1);
2042 *rLo = iselIntExpr_R(env, e->Iex.Binop.arg2);
2057 HReg dstHi = newVRegI(env);
2058 HReg dstLo = newVRegI(env);
2059 HReg src = iselDblExpr(env, e->Iex.Unop.arg);
2060 addInstr(env, ARMInstr_VXferD(False/*!toD*/, src, dstHi, dstLo));
2069 HReg tHi = newVRegI(env);
2070 HReg tLo = newVRegI(env);
2071 HReg zero = newVRegI(env);
2073 iselInt64Expr(&yHi, &yLo, env, e->Iex.Unop.arg);
2075 addInstr(env, ARMInstr_Imm32(zero, 0));
2077 addInstr(env, ARMInstr_Alu(ARMalu_SUBS,
2080 addInstr(env, ARMInstr_Alu(ARMalu_SBC,
2085 addInstr(env, ARMInstr_Alu(ARMalu_OR, tHi, tHi, ARMRI84_R(yHi)));
2086 addInstr(env, ARMInstr_Alu(ARMalu_OR, tLo, tLo, ARMRI84_R(yLo)));
2095 HReg tmp1 = newVRegI(env);
2096 HReg tmp2 = newVRegI(env);
2098 iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg);
2100 addInstr(env, ARMInstr_Alu(ARMalu_OR,
2103 addInstr(env, ARMInstr_Unary(ARMun_NEG, tmp2, tmp1));
2104 addInstr(env, ARMInstr_Alu(ARMalu_OR,
2106 addInstr(env, ARMInstr_Shift(ARMsh_SAR,
2114 HReg dst = newVRegI(env);
2115 ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg);
2120 addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0)));
2121 addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0)));
2122 addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, dst, amt));
2123 addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, amt));
2139 tyC = typeOfIRExpr(env->type_env,e->Iex.ITE.cond);
2141 iselInt64Expr(&r1hi, &r1lo, env, e->Iex.ITE.iftrue);
2142 iselInt64Expr(&r0hi, &r0lo, env, e->Iex.ITE.iffalse);
2143 dstHi = newVRegI(env);
2144 dstLo = newVRegI(env);
2145 addInstr(env, mk_iMOVds_RR(dstHi, r1hi));
2146 addInstr(env, mk_iMOVds_RR(dstLo, r1lo));
2147 cc = iselCondCode(env, e->Iex.ITE.cond);
2148 addInstr(env, ARMInstr_CMov(cc ^ 1, dstHi, ARMRI84_R(r0hi)));
2149 addInstr(env, ARMInstr_CMov(cc ^ 1, dstLo, ARMRI84_R(r0lo)));
2158 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
2159 HReg tHi = newVRegI(env);
2160 HReg tLo = newVRegI(env);
2161 HReg tmp = iselNeon64Expr(env, e);
2162 addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo));
2177 static HReg iselNeon64Expr ( ISelEnv* env, IRExpr* e )
2180 vassert(env->hwcaps & VEX_HWCAPS_ARM_NEON);
2181 r = iselNeon64Expr_wrk( env, e );
2188 static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e )
2190 IRType ty = typeOfIRExpr(env->type_env, e);
2196 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
2201 HReg res = newVRegD(env);
2202 iselInt64Expr(&rHi, &rLo, env, e);
2203 addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
2209 HReg res = newVRegD(env);
2210 ARMAModeN* am = iselIntExpr_AModeN(env, e->Iex.Load.addr);
2212 addInstr(env, ARMInstr_NLdStD(True, res, am));
2218 HReg addr = newVRegI(env);
2219 HReg res = newVRegD(env);
2221 addInstr(env, ARMInstr_Add32(addr, hregARM_R8(), e->Iex.Get.offset));
2222 addInstr(env, ARMInstr_NLdStD(True, res, mkARMAModeN_R(addr)));
2234 HReg res = newVRegD(env);
2235 iselInt64Expr(&rHi, &rLo, env, e);
2236 addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
2241 HReg res = newVRegD(env);
2242 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2243 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2244 addInstr(env, ARMInstr_NBinary(ARMneon_VAND,
2249 HReg res = newVRegD(env);
2250 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2251 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2252 addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
2257 HReg res = newVRegD(env);
2258 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2259 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2260 addInstr(env, ARMInstr_NBinary(ARMneon_VXOR,
2267 HReg rHi = iselIntExpr_R(env, e->Iex.Binop.arg1);
2268 HReg rLo = iselIntExpr_R(env, e->Iex.Binop.arg2);
2269 HReg res = newVRegD(env);
2270 addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
2278 HReg res = newVRegD(env);
2279 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2280 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2289 addInstr(env, ARMInstr_NBinary(ARMneon_VADD,
2294 HReg res = newVRegD(env);
2295 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2296 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2298 addInstr(env, ARMInstr_NBinary(ARMneon_VADDFP,
2303 HReg res = newVRegD(env);
2304 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2305 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2307 addInstr(env, ARMInstr_NBinary(ARMneon_VRECPS,
2312 HReg res = newVRegD(env);
2313 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2314 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2316 addInstr(env, ARMInstr_NBinary(ARMneon_VRSQRTS,
2328 HReg rD = newVRegD(env);
2329 HReg rM = newVRegD(env);
2330 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2331 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2343 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, False));
2344 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, False));
2345 addInstr(env, ARMInstr_NDual(ARMneon_TRN, rD, rM, size, False));
2354 HReg rD = newVRegD(env);
2355 HReg rM = newVRegD(env);
2356 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2357 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2367 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, False));
2368 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, False));
2369 addInstr(env, ARMInstr_NDual(ARMneon_ZIP, rD, rM, size, False));
2378 HReg rD = newVRegD(env);
2379 HReg rM = newVRegD(env);
2380 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2381 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2391 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, False));
2392 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, False));
2393 addInstr(env, ARMInstr_NDual(ARMneon_UZP, rD, rM, size, False));
2401 HReg res = newVRegD(env);
2402 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2403 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2412 addInstr(env, ARMInstr_NBinary(ARMneon_VQADDU,
2420 HReg res = newVRegD(env);
2421 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2422 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2431 addInstr(env, ARMInstr_NBinary(ARMneon_VQADDS,
2439 HReg res = newVRegD(env);
2440 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2441 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2450 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
2455 HReg res = newVRegD(env);
2456 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2457 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2459 addInstr(env, ARMInstr_NBinary(ARMneon_VSUBFP,
2467 HReg res = newVRegD(env);
2468 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2469 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2478 addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBU,
2486 HReg res = newVRegD(env);
2487 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2488 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2497 addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBS,
2504 HReg res = newVRegD(env);
2505 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2506 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2514 addInstr(env, ARMInstr_NBinary(ARMneon_VMAXU,
2521 HReg res = newVRegD(env);
2522 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2523 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2531 addInstr(env, ARMInstr_NBinary(ARMneon_VMAXS,
2538 HReg res = newVRegD(env);
2539 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2540 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2548 addInstr(env, ARMInstr_NBinary(ARMneon_VMINU,
2555 HReg res = newVRegD(env);
2556 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2557 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2565 addInstr(env, ARMInstr_NBinary(ARMneon_VMINS,
2572 HReg res = newVRegD(env);
2573 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2574 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2575 HReg argR2 = newVRegD(env);
2576 HReg zero = newVRegD(env);
2585 addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
2586 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
2588 addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
2596 HReg res = newVRegD(env);
2597 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2598 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2607 addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
2614 HReg res = newVRegD(env);
2615 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2616 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2617 HReg argR2 = newVRegD(env);
2618 HReg zero = newVRegD(env);
2626 addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
2627 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
2629 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
2636 HReg res = newVRegD(env);
2637 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2638 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2646 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
2654 HReg res = newVRegD(env);
2655 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2656 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2665 addInstr(env, ARMInstr_NShift(ARMneon_VQSHL,
2673 HReg res = newVRegD(env);
2674 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2675 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2684 addInstr(env, ARMInstr_NShift(ARMneon_VQSAL,
2692 HReg res = newVRegD(env);
2693 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2696 typeOfIRExpr(env
2708 addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU,
2716 HReg res = newVRegD(env);
2717 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2720 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
2732 addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS,
2740 HReg res = newVRegD(env);
2741 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2744 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
2756 addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS,
2764 HReg res = newVRegD(env);
2765 HReg tmp = newVRegD(env);
2766 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2767 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
2768 HReg argR2 = newVRegI(env);
2777 addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR));
2778 addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, False));
2779 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
2787 HReg res = newVRegD(env);
2788 HReg tmp = newVRegD(env);
2789 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2797 addInstr(env, ARMInstr_NShl64(res, argL, nshift));
2802 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
2811 addInstr(env, ARMInstr_NUnary(ARMneon_DUP,
2813 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
2821 HReg res = newVRegD(env);
2822 HReg tmp = newVRegD(env);
2823 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2824 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
2825 HReg argR2 = newVRegI(env);
2834 addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR));
2835 addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, False));
2836 addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
2843 HReg res = newVRegD(env);
2844 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2845 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2853 addInstr(env, ARMInstr_NBinary(ARMneon_VCGTU,
2860 HReg res = newVRegD(env);
2861 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2862 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2870 addInstr(env, ARMInstr_NBinary(ARMneon_VCGTS,
2877 HReg res = newVRegD(env);
2878 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2879 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2887 addInstr(env, ARMInstr_NBinary(ARMneon_VCEQ,
2894 HReg res = newVRegD(env);
2895 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2896 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2904 addInstr(env, ARMInstr_NBinary(ARMneon_VMUL,
2909 HReg res = newVRegD(env);
2910 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2911 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2913 addInstr(env, ARMInstr_NBinary(ARMneon_VMULFP,
2919 HReg res = newVRegD(env);
2920 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2921 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2928 addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULH,
2935 HReg res = newVRegD(env);
2936 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2937 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2944 addInstr(env, ARMInstr_NBinary(ARMneon_VQRDMULH,
2952 HReg res = newVRegD(env);
2953 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2954 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2962 addInstr(env, ARMInstr_NBinary(ARMneon_VPADD,
2967 HReg res = newVRegD(env);
2968 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2969 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2971 addInstr(env, ARMInstr_NBinary(ARMneon_VPADDFP,
2978 HReg res = newVRegD(env);
2979 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2980 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2988 addInstr(env, ARMInstr_NBinary(ARMneon_VPMINU,
2995 HReg res = newVRegD(env);
2996 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2997 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
3005 addInstr(env, ARMInstr_NBinary(ARMneon_VPMINS,
3012 HReg res = newVRegD(env);
3013 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3014 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
3022 addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXU,
3029 HReg res = newVRegD(env);
3030 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3031 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
3039 addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXS,
3044 HReg res = newVRegD(env);
3045 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3046 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
3047 addInstr(env, ARMInstr_NBinary(ARMneon_VTBL,
3052 HReg res = newVRegD(env);
3053 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3054 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
3056 addInstr(env, ARMInstr_NBinary(ARMneon_VMULP,
3061 HReg res = newVRegD(env);
3062 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3063 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
3064 addInstr(env, ARMInstr_NBinary(ARMneon_VMAXF,
3069 HReg res = newVRegD(env);
3070 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3071 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
3072 addInstr(env, ARMInstr_NBinary(ARMneon_VMINF,
3077 HReg res = newVRegD(env);
3078 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3079 HReg argR = iselNeon64Expr(env
3080 addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXF,
3085 HReg res = newVRegD(env);
3086 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3087 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
3088 addInstr(env, ARMInstr_NBinary(ARMneon_VPMINF,
3093 HReg res = newVRegD(env);
3094 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3095 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
3096 addInstr(env, ARMInstr_NBinary(ARMneon_VCGTF,
3101 HReg res = newVRegD(env);
3102 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3103 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
3104 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEF,
3109 HReg res = newVRegD(env);
3110 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3111 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
3112 addInstr(env, ARMInstr_NBinary(ARMneon_VCEQF,
3120 HReg res = newVRegD(env);
3121 HReg arg = iselNeon64Expr(env, e->Iex.Binop.arg1);
3125 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
3139 addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, False));
3147 HReg res = newVRegD(env);
3148 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3153 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
3168 addInstr(env, ARMInstr_NUnary(ARMneon_VDUP,
3184 HReg rLo = iselIntExpr_R(env, e->Iex.Unop.arg);
3185 HReg rHi = newVRegI(env);
3186 HReg res = newVRegD(env);
3187 addInstr(env, ARMInstr_Imm32(rHi, 0));
3188 addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
3194 HReg rLo = iselIntExpr_R(env, e->Iex.Unop.arg);
3195 HReg rHi = newVRegI(env);
3196 addInstr(env, mk_iMOVds_RR(rHi, rLo));
3197 addInstr(env, ARMInstr_Shift(ARMsh_SAR, rHi, rHi, ARMRI5_I5(31)));
3198 HReg res = newVRegD(env);
3199 addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
3211 HReg res = newVRegD(env);
3212 iselInt64Expr(&rHi, &rLo, env, e);
3213 addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
3246 HReg res = newVRegD(env);
3247 HReg arg = iselNeon64Expr(env, mi.bindee[0]);
3248 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 0, False));
3251 HReg res = newVRegD(env);
3252 HReg arg = iselNeon64Expr(env, mi.bindee[0]);
3253 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 1, False));
3256 HReg res = newVRegD(env);
3257 HReg arg = iselNeon64Expr(env, mi.bindee[0]);
3258 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 2, False));
3261 HReg res = newVRegD(env);
3262 HReg argL = iselNeon64Expr(env, mi.bindee[0]);
3263 HReg argR = iselNeon64Expr(env, mi.bindee[1]);
3264 addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
3268 HReg res = newVRegD(env);
3269 HReg argL = iselNeon64Expr(env, mi.bindee[0]);
3270 HReg argR = iselNeon64Expr(env, mi.bindee[1]);
3271 addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
3275 HReg res = newVRegD(env);
3276 HReg argL = iselNeon64Expr(env, mi.bindee[0]);
3277 HReg argR = iselNeon64Expr(env, mi.bindee[1]);
3278 addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
3282 HReg res = newVRegD(env);
3283 HReg argL = iselNeon64Expr(env, mi.bindee[0]);
3284 HReg argR = iselNeon64Expr(env, mi.bindee[1]);
3285 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
3289 HReg res = newVRegD(env);
3290 HReg argL = iselNeon64Expr(env, mi.bindee[0]);
3291 HReg argR = iselNeon64Expr(env, mi.bindee[1]);
3292 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
3296 HReg res = newVRegD(env);
3297 HReg argL = iselNeon64Expr(env, mi.bindee[0]);
3298 HReg argR = iselNeon64Expr(env, mi.bindee[1]);
3299 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
3303 HReg res = newVRegD(env);
3304 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3305 addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, arg, 4, False));
3327 typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
3331 res = newVRegD(env);
3332 arg = iselNeon64Expr(env, mi.bindee[0]);
3333 addInstr(env, ARMInstr_NUnaryS(
3346 typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
3350 res = newVRegD(env);
3351 arg = iselNeon64Expr(env, mi.bindee[0]);
3352 addInstr(env, ARMInstr_NUnaryS(
3365 typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
3369 res = newVRegD(env);
3370 arg = iselNeon64Expr(env, mi.bindee[0]);
3371 addInstr(env, ARMInstr_NUnaryS(
3381 arg = iselIntExpr_R(env, e->Iex.Unop.arg);
3382 res = newVRegD(env);
3389 addInstr(env, ARMInstr_NUnary(ARMneon_DUP, res, arg, size, False));
3395 HReg res = newVRegD(env);
3396 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3404 addInstr(env, ARMInstr_NUnary(ARMneon_ABS, res, arg, size, False));
3410 HReg res = newVRegD(env);
3411 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3419 addInstr(env, ARMInstr_NUnary(ARMneon_REV64,
3425 HReg res = newVRegD(env);
3426 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3433 addInstr(env, ARMInstr_NUnary(ARMneon_REV32,
3438 HReg res = newVRegD(env);
3439 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3441 addInstr(env, ARMInstr_NUnary(ARMneon_REV16,
3446 HReg x_lsh = newVRegD(env);
3447 HReg x_rsh = newVRegD(env);
3448 HReg lsh_amt = newVRegD(env);
3449 HReg rsh_amt = newVRegD(env);
3450 HReg zero = newVRegD(env);
3451 env);
3452 HReg tmp2 = newVRegD(env);
3453 HReg res = newVRegD(env);
3454 HReg x = newVRegD(env);
3455 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3456 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp2, arg, 2, False));
3457 addInstr(env, ARMInstr_NUnary(ARMneon_NOT, x, tmp2, 4, False));
3458 addInstr(env, ARMInstr_NeonImm(lsh_amt, ARMNImm_TI(0, 32)));
3459 addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0, 0)));
3460 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
3462 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
3464 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
3466 addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
3468 addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
3475 HReg res = newVRegD(env);
3476 HReg tmp = newVRegD(env);
3477 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3485 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp, arg, size, False));
3486 addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, tmp, 4, False));
3492 HReg res = newVRegD(env);
3493 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3501 addInstr(env, ARMInstr_NUnary(ARMneon_COPYN,
3508 HReg res = newVRegD(env);
3509 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3517 addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNSS,
3524 HReg res = newVRegD(env);
3525 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3533 addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUS,
3540 HReg res = newVRegD(env);
3541 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3549 addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUU,
3556 HReg res = newVRegD(env);
3557 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3565 addInstr(env, ARMInstr_NUnary(ARMneon_PADDLS,
3572 HReg res = newVRegD(env);
3573 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3581 addInstr(env, ARMInstr_NUnary(ARMneon_PADDLU,
3586 HReg res = newVRegD(env);
3587 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3589 addInstr(env, ARMInstr_NUnary(ARMneon_CNT,
3596 HReg res = newVRegD(env);
3597 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3605 addInstr(env, ARMInstr_NUnary(ARMneon_CLZ,
3612 HReg res = newVRegD(env);
3613 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3621 addInstr(env, ARMInstr_NUnary(ARMneon_CLS,
3626 HReg res = newVRegD(env);
3627 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3628 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS,
3633 HReg res = newVRegD(env);
3634 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3635 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU,
3640 HReg res = newVRegD(env);
3641 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3642 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF,
3647 HReg res = newVRegD(env);
3648 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3649 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF,
3654 HReg res = newVRegD(env);
3655 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3656 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTF32toF16,
3661 HReg res = newVRegD(env);
3662 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3663 addInstr(env, ARMInstr_NUnary(ARMneon_VRECIPF,
3668 HReg res = newVRegD(env);
3669 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3670 addInstr(env, ARMInstr_NUnary(ARMneon_VRECIP,
3682 HReg res = newVRegD(env);
3683 HReg argL = iselNeon64Expr(env, mi.bindee[0]);
3684 HReg argR = iselNeon64Expr(env, mi.bindee[1]);
3685 addInstr(env, ARMInstr_NBinary(ARMneon_VABDFP,
3689 HReg res = newVRegD(env);
3690 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3691 addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP,
3697 HReg res = newVRegD(env);
3698 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3699 addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTEFP,
3704 HReg res = newVRegD(env);
3705 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3706 addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTE,
3711 HReg res = newVRegD(env);
3712 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3713 addInstr(env, ARMInstr_NUnary(ARMneon_VNEGF,
3727 HReg res = newVRegD(env);
3728 HReg argL = iselNeon64Expr(env, triop->arg2);
3729 HReg argR = iselNeon64Expr(env, triop->arg1);
3732 typeOfIRExpr(env->type_env, triop->arg3) != Ity_I8) {
3741 addInstr(env, ARMInstr_NBinary(ARMneon_VEXT,
3748 HReg res = newVRegD(env);
3749 HReg dreg = iselNeon64Expr(env, triop->arg1);
3750 HReg arg = iselIntExpr_R(env, triop->arg3);
3753 typeOfIRExpr(env->type_env, triop->arg2) != Ity_I8) {
3764 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, res, dreg, 4, False));
3765 addInstr(env, ARMInstr_NUnaryS(ARMneon_SETELEM,
3779 HReg res = newVRegD(env);
3780 iselInt64Expr(&rHi, &rLo, env, e);
3781 addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
3790 static HReg iselNeonExpr ( ISelEnv* env, IRExpr* e )
3793 vassert(env->hwcaps & VEX_HWCAPS_ARM_NEON);
3794 r = iselNeonExpr_wrk( env, e );
3801 static HReg iselNeonExpr_wrk ( ISelEnv* env, IRExpr* e )
3803 IRType ty = typeOfIRExpr(env->type_env, e);
3809 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
3818 HReg res = newVRegV(env);
3819 addInstr(env, ARMInstr_NeonImm(res, ARMNImm_TI(6, 0)));
3823 HReg res = newVRegV(env);
3824 addInstr(env, ARMInstr_NeonImm(res, ARMNImm_TI(6, 255)));
3832 HReg res = newVRegV(env);
3833 ARMAModeN* am = iselIntExpr_AModeN(env, e->Iex.Load.addr);
3835 addInstr(env, ARMInstr_NLdStQ(True, res, am));
3840 HReg addr = newVRegI(env);
3841 HReg res = newVRegV(env);
3843 addInstr(env, ARMInstr_Add32(addr, hregARM_R8(), e->Iex.Get.offset));
3844 addInstr(env, ARMInstr_NLdStQ(True, res, mkARMAModeN_R(addr)));
3879 HReg res = newVRegV(env);
3880 HReg arg = iselNeonExpr(env, mi.bindee[0]);
3881 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 0, True));
3884 HReg res = newVRegV(env);
3885 HReg arg = iselNeonExpr(env, mi.bindee[0]);
3886 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 1, True));
3889 HReg res = newVRegV(env);
3890 HReg arg = iselNeonExpr(env, mi.bindee[0]);
3891 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 2, True));
3894 HReg res = newVRegV(env);
3895 HReg argL = iselNeonExpr(env, mi.bindee[0]);
3896 HReg argR = iselNeonExpr(env, mi.bindee[1]);
3897 addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
3901 HReg res = newVRegV(env);
3902 HReg argL = iselNeonExpr(env, mi.bindee[0]);
3903 HReg argR = iselNeonExpr(env, mi.bindee[1]);
3904 addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
3908 HReg res = newVRegV(env);
3909 HReg argL = iselNeonExpr(env, mi.bindee[0]);
3910 HReg argR = iselNeonExpr(env, mi.bindee[1]);
3911 addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
3915 HReg res = newVRegV(env);
3916 HReg argL = iselNeonExpr(env, mi.bindee[0]);
3917 HReg argR = iselNeonExpr(env, mi.bindee[1]);
3918 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
3922 HReg res = newVRegV(env);
3923 HReg argL = iselNeonExpr(env, mi.bindee[0]);
3924 HReg argR = iselNeonExpr(env, mi.bindee[1]);
3925 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
3929 HReg res = newVRegV(env);
3930 HReg argL = iselNeonExpr(env, mi.bindee[0]);
3931 HReg argR = iselNeonExpr(env, mi.bindee[1]);
3932 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
3936 HReg res = newVRegV(env);
3937 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3938 addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, arg, 4, True));
3960 typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
3964 res = newVRegV(env);
3965 arg = iselNeon64Expr(env, mi.bindee[0]);
3966 addInstr(env, ARMInstr_NUnaryS(
3979 typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
3983 res = newVRegV(env);
3984 arg = iselNeon64Expr(env, mi.bindee[0]);
3985 addInstr(env, ARMInstr_NUnaryS(
3998 typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
4002 res = newVRegV(env);
4003 arg = iselNeon64Expr(env, mi.bindee[0]);
4004 addInstr(env, ARMInstr_NUnaryS(
4014 arg = iselIntExpr_R(env, e->Iex.Unop.arg);
4015 res = newVRegV(env);
4022 addInstr(env, ARMInstr_NUnary(ARMneon_DUP, res, arg, size, True));
4028 HReg res = newVRegV(env);
4029 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4037 addInstr(env, ARMInstr_NUnary(ARMneon_ABS, res, arg, size, True));
4043 HReg res = newVRegV(env);
4044 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4052 addInstr(env, ARMInstr_NUnary(ARMneon_REV64,
4058 HReg res = newVRegV(env);
4059 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4066 addInstr(env, ARMInstr_NUnary(ARMneon_REV32,
4071 HReg res = newVRegV(env);
4072 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4074 addInstr(env, ARMInstr_NUnary(ARMneon_REV16,
4079 HReg x_lsh = newVRegV(env);
4080 HReg x_rsh = newVRegV(env);
4081 HReg lsh_amt = newVRegV(env);
4082 HReg rsh_amt = newVRegV(env);
4083 HReg zero = newVRegV(env);
4084 HReg tmp = newVRegV(env);
4085 HReg tmp2 = newVRegV(env);
4086 HReg res = newVRegV(env);
4087 HReg x = newVRegV(env);
4088 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4089 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp2, arg, 2, True));
4090 addInstr(env, ARMInstr_NUnary(ARMneon_NOT, x, tmp2, 4, True));
4091 addInstr(env, ARMInstr_NeonImm(lsh_amt, ARMNImm_TI(0, 32)));
4092 addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0, 0)));
4093 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
4095 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
4097 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
4099 addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
4101 addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
4108 HReg res = newVRegV(env);
4109 HReg tmp = newVRegV(env);
4110 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4118 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp, arg, size, True));
4119 addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, tmp, 4, True));
4125 HReg res = newVRegV(env);
4126 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
4134 addInstr(env, ARMInstr_NUnary(ARMneon_COPYLU,
4141 HReg res = newVRegV(env);
4142 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
4150 addInstr(env, ARMInstr_NUnary(ARMneon_COPYLS,
4157 HReg res = newVRegV(env);
4158 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4166 addInstr(env, ARMInstr_NUnary(ARMneon_PADDLS,
4173 HReg res = newVRegV(env);
4174 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4182 addInstr(env, ARMInstr_NUnary(ARMneon_PADDLU,
4187 HReg res = newVRegV(env);
4188 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4190 addInstr(env, ARMInstr_NUnary(ARMneon_CNT, res, arg, size, True));
4196 HReg res = newVRegV(env);
4197 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4205 addInstr(env, ARMInstr_NUnary(ARMneon_CLZ, res, arg, size, True));
4211 HReg res = newVRegV(env);
4212 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4220 addInstr(env, ARMInstr_NUnary(ARMneon_CLS, res, arg, size, True));
4224 HReg res = newVRegV(env);
4225 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4226 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS,
4231 HReg res = newVRegV(env);
4232 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4233 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU,
4238 HReg res = newVRegV(env);
4239 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4240 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF,
4245 HReg res = newVRegV(env);
4246 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4247 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF,
4252 HReg res = newVRegV(env);
4253 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
4254 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTF16toF32,
4259 HReg res = newVRegV(env);
4260 HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
4261 addInstr(env, ARMInstr_NUnary(ARMneon_VRECIPF,
4266 HReg res = newVRegV(env);
4267 HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
4268 addInstr(env, ARMInstr_NUnary(ARMneon_VRECIP,
4273 HReg res = newVRegV(env);
4274 HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
4275 addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP,
4280 HReg res = newVRegV(env);
4281 HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
4282 addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTEFP,
4287 HReg res = newVRegV(env);
4288 HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
4289 addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTE,
4294 HReg res = newVRegV(env);
4295 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4296 addInstr(env, ARMInstr_NUnary(ARMneon_VNEGF,
4312 typeOfIRExpr(env->type_env, e->Iex.Binop.arg1) == Ity_I64 &&
4313 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) == Ity_I64 &&
4319 HReg res = newVRegV(env);
4320 addInstr(env, ARMInstr_NeonImm(res, imm));
4325 HReg tmp1 = newVRegV(env);
4326 HReg tmp2 = newVRegV(env);
4327 HReg res = newVRegV(env);
4329 addInstr(env, ARMInstr_NeonImm(tmp1, ARMNImm_TI(9,0x0f)));
4330 addInstr(env, ARMInstr_NeonImm(tmp2, imm));
4331 addInstr(env, ARMInstr_NBinary(ARMneon_VAND,
4338 HReg tmp1 = newVRegV(env);
4339 HReg tmp2 = newVRegV(env);
4340 HReg res = newVRegV(env);
4342 addInstr(env, ARMInstr_NeonImm(tmp1, ARMNImm_TI(9,0xf0)));
4343 addInstr(env, ARMInstr_NeonImm(tmp2, imm));
4344 addInstr(env, ARMInstr_NBinary(ARMneon_VAND,
4357 HReg res = newVRegV(env);
4364 addInstr(env, ARMInstr_Alu(ARMalu_SUB, hregARM_R13(),
4368 iselInt64Expr(&w1, &w0, env, e->Iex.Binop.arg2);
4369 addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*store*/,
4371 addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*store*/,
4375 iselInt64Expr(&w3, &w2, env, e->Iex.Binop.arg1);
4376 addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*store*/,
4378 addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*store*/,
4382 addInstr(env, ARMInstr_NLdStQ(True/*load*/, res,
4386 addInstr(env, ARMInstr_Alu(ARMalu_ADD, hregARM_R13(),
4392 HReg res = newVRegV(env);
4393 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4394 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4395 addInstr(env, ARMInstr_NBinary(ARMneon_VAND,
4400 HReg res = newVRegV(env);
4401 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4402 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4403 addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
4408 HReg res = newVRegV(env);
4409 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4410 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4411 addInstr(env, ARMInstr_NBinary(ARMneon_VXOR,
4444 HReg res = newVRegV(env);
4445 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4446 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4457 addInstr(env, ARMInstr_NBinary(ARMneon_VADD,
4462 HReg res = newVRegV(env);
4463 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4464 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4466 addInstr(env, ARMInstr_NBinary(ARMneon_VRECPS,
4471 HReg res = newVRegV(env);
4472 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4473 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4475 addInstr(env, ARMInstr_NBinary(ARMneon_VRSQRTS,
4487 HReg rD = newVRegV(env);
4488 HReg rM = newVRegV(env);
4489 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4490 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4502 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, True));
4503 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, True));
4504 addInstr(env, ARMInstr_NDual(ARMneon_TRN, rD, rM, size, True));
4515 HReg rD = newVRegV(env);
4516 HReg rM = newVRegV(env);
4517 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4518 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4530 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, True));
4531 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, True));
4532 addInstr(env, ARMInstr_NDual(ARMneon_ZIP, rD, rM, size, True));
4543 HReg rD = newVRegV(env);
4544 HReg rM = newVRegV(env);
4545 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4546 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4558 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rM, argL, 4, True));
4559 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, rD, argR, 4, True));
4560 addInstr(env, ARMInstr_NDual(ARMneon_UZP, rD, rM, size, True));
4568 HReg res = newVRegV(env);
4569 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4570 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4581 addInstr(env, ARMInstr_NBinary(ARMneon_VQADDU,
4589 HReg res = newVRegV(env);
4590 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4591 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4602 addInstr(env, ARMInstr_NBinary(ARMneon_VQADDS,
4610 HReg res = newVRegV(env);
4611 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4612 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4623 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
4631 HReg res = newVRegV(env);
4632 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4633 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4644 addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBU,
4652 HReg res = newVRegV(env);
4653 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4654 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4665 addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBS,
4672 HReg res = newVRegV(env);
4673 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4674 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4682 addInstr(env, ARMInstr_NBinary(ARMneon_VMAXU,
4689 HReg res = newVRegV(env);
4690 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4691 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4699 addInstr(env, ARMInstr_NBinary(ARMneon_VMAXS,
4706 HReg res = newVRegV(env);
4707 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4708 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4716 addInstr(env, ARMInstr_NBinary(ARMneon_VMINU,
4723 HReg res = newVRegV(env);
4724 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4725 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4733 addInstr(env, ARMInstr_NBinary(ARMneon_VMINS,
4741 HReg res = newVRegV(env);
4742 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4743 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4744 HReg argR2 = newVRegV(env);
4745 HReg zero = newVRegV(env);
4754 addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
4755 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
4757 addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
4765 HReg res = newVRegV(env);
4766 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4767 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4776 addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
4784 HReg res = newVRegV(env);
4785 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4786 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4787 HReg argR2 = newVRegV(env);
4788 HReg zero = newVRegV(env);
4797 addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
4798 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
4800 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
4808 HReg res = newVRegV(env);
4809 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4810 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4819 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
4827 HReg res = newVRegV(env);
4828 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4829 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4838 addInstr(env, ARMInstr_NShift(ARMneon_VQSHL,
4846 HReg res = newVRegV(env);
4847 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4848 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4857 addInstr(env, ARMInstr_NShift(ARMneon_VQSAL,
4865 HReg res = newVRegV(env);
4866 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4869 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
4881 addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU,
4889 HReg res = newVRegV(env);
4890 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4893 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
4905 addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS,
4913 HReg res = newVRegV(env);
4914 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4917 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
4929 addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS,
4937 HReg res = newVRegV(env);
4938 HReg tmp = newVRegV(env);
4939 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4940 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
4941 HReg argR2 = newVRegI(env);
4950 addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR));
4951 addInstr(env, ARMInstr_NUnary(ARMneon_DUP,
4953 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
4961 HReg res = newVRegV(env);
4962 HReg tmp = newVRegV(env);
4963 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4964 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
4973 addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR, 0, True));
4974 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
4982 HReg res = newVRegV(env);
4983 env);
4984 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4985 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
4986 HReg argR2 = newVRegI(env);
4995 addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR));
4996 addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, True));
4997 addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
5004 HReg res = newVRegV(env);
5005 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5006 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5014 addInstr(env, ARMInstr_NBinary(ARMneon_VCGTU,
5021 HReg res = newVRegV(env);
5022 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5023 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5031 addInstr(env, ARMInstr_NBinary(ARMneon_VCGTS,
5038 HReg res = newVRegV(env);
5039 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5040 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5048 addInstr(env, ARMInstr_NBinary(ARMneon_VCEQ,
5055 HReg res = newVRegV(env);
5056 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5057 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5065 addInstr(env, ARMInstr_NBinary(ARMneon_VMUL,
5072 HReg res = newVRegV(env);
5073 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
5074 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
5082 addInstr(env, ARMInstr_NBinary(ARMneon_VMULLU,
5090 HReg res = newVRegV(env);
5091 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
5092 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
5100 addInstr(env, ARMInstr_NBinary(ARMneon_VMULLS,
5107 HReg res = newVRegV(env);
5108 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5109 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5116 addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULH,
5123 HReg res = newVRegV(env);
5124 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5125 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5132 addInstr(env, ARMInstr_NBinary(ARMneon_VQRDMULH,
5139 HReg res = newVRegV(env);
5140 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
5141 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
5148 addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULL,
5153 HReg res = newVRegV(env);
5154 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5155 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5157 addInstr(env, ARMInstr_NBinary(ARMneon_VMULP,
5162 HReg res = newVRegV(env);
5163 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5164 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5165 addInstr(env, ARMInstr_NBinary(ARMneon_VMAXF,
5170 HReg res = newVRegV(env);
5171 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5172 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5173 addInstr(env, ARMInstr_NBinary(ARMneon_VMINF,
5178 HReg res = newVRegV(env);
5179 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5180 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5181 addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXF,
5186 HReg res = newVRegV(env);
5187 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5188 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5189 addInstr(env, ARMInstr_NBinary(ARMneon_VPMINF,
5194 HReg res = newVRegV(env);
5195 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5196 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5197 addInstr(env, ARMInstr_NBinary(ARMneon_VCGTF,
5202 HReg res = newVRegV(env);
5203 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5204 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5205 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEF,
5210 HReg res = newVRegV(env);
5211 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5212 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5213 addInstr(env, ARMInstr_NBinary(ARMneon_VCEQF,
5219 HReg res = newVRegV(env);
5220 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
5221 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
5223 addInstr(env, ARMInstr_NBinary(ARMneon_VMULLP,
5231 HReg res = newVRegV(env);
5232 HReg arg = iselNeonExpr(env, e->Iex.Binop.arg1);
5236 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
5250 addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, True));
5258 HReg res = newVRegV(env);
5259 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
5263 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
5278 addInstr(env, ARMInstr_NUnary(ARMneon_VDUP,
5286 HReg res = newVRegV(env);
5287 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5288 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5296 addInstr(env, ARMInstr_NBinary(ARMneon_VPADD,
5311 HReg res = newVRegV(env);
5312 HReg argL = iselNeonExpr(env, triop->arg2);
5313 HReg argR = iselNeonExpr(env, triop->arg1);
5316 typeOfIRExpr(env->type_env, triop->arg3) != Ity_I8) {
5325 addInstr(env, ARMInstr_NBinary(ARMneon_VEXT,
5332 HReg res = newVRegV(env);
5333 HReg argL = iselNeonExpr(env, triop->arg2);
5334 HReg argR = iselNeonExpr(env, triop->arg3);
5343 addInstr(env, ARMInstr_NBinary(op, res, argL, argR, size, True));
5353 HReg r1 = iselNeonExpr(env, e->Iex.ITE.iftrue);
5354 HReg r0 = iselNeonExpr(env, e->Iex.ITE.iffalse);
5355 HReg dst = newVRegV(env);
5356 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, dst, r1, 4, True));
5357 cc = iselCondCode(env, e->Iex.ITE.cond);
5358 addInstr(env, ARMInstr_NCMovQ(cc ^ 1, dst, r0));
5376 static HReg iselDblExpr ( ISelEnv* env, IRExpr* e )
5378 HReg r = iselDblExpr_wrk( env, e );
5388 static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e )
5390 IRType ty = typeOfIRExpr(env->type_env,e);
5395 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
5402 HReg z32 = newVRegI(env);
5403 HReg dst = newVRegD(env);
5404 addInstr(env, ARMInstr_Imm32(z32, 0));
5405 addInstr(env, ARMInstr_VXferD(True/*toD*/, dst, z32, z32));
5412 HReg res = newVRegD(env);
5414 am = iselIntExpr_AModeV(env, e->Iex.Load.addr);
5415 addInstr(env, ARMInstr_VLdStD(True/*isLoad*/, res, am));
5423 HReg res = newVRegD(env);
5424 addInstr(env, ARMInstr_VLdStD(True/*isLoad*/, res, am));
5431 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
5432 return iselNeon64Expr(env, e->Iex.Unop.arg);
5435 HReg dst = newVRegD(env);
5436 iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg);
5437 addInstr(env, ARMInstr_VXferD(True/*toD*/, dst, srcHi, srcLo));
5442 HReg src = iselDblExpr(env, e->Iex.Unop.arg);
5443 HReg dst = newVRegD(env);
5444 addInstr(env, ARMInstr_VUnaryD(ARMvfpu_NEG, dst, src));
5448 HReg src = iselDblExpr(env, e->Iex.Unop.arg);
5449 HReg dst = newVRegD(env);
5450 addInstr(env, ARMInstr_VUnaryD(ARMvfpu_ABS, dst, src));
5454 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
5455 HReg dst = newVRegD(env);
5456 addInstr(env, ARMInstr_VCvtSD(True/*sToD*/, dst, src));
5461 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
5462 HReg f32 = newVRegF(env);
5463 HReg dst = newVRegD(env);
5466 addInstr(env, ARMInstr_VXferS(True/*toS*/, f32, src));
5468 addInstr(env, ARMInstr_VCvtID(True/*iToD*/, syned,
5481 HReg src = iselDblExpr(env, e->Iex.Binop.arg2);
5482 HReg dst = newVRegD(env);
5483 addInstr(env, ARMInstr_VUnaryD(ARMvfpu_SQRT, dst, src));
5500 HReg argL = iselDblExpr(env, triop->arg2);
5501 HReg argR = iselDblExpr(env, triop->arg3);
5502 HReg dst = newVRegD(env);
5510 addInstr(env, ARMInstr_VAluD(op, dst, argL, argR));
5520 && typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1) {
5521 HReg r1 = iselDblExpr(env, e->Iex.ITE.iftrue);
5522 HReg r0 = iselDblExpr(env, e->Iex.ITE.iffalse);
5523 HReg dst = newVRegD(env);
5524 addInstr(env, ARMInstr_VUnaryD(ARMvfpu_COPY, dst, r1));
5525 ARMCondCode cc = iselCondCode(env, e->Iex.ITE.cond);
5526 addInstr(env, ARMInstr_VCMovD(cc ^ 1, dst, r0));
5545 static HReg iselFltExpr ( ISelEnv* env, IRExpr* e )
5547 HReg r = iselFltExpr_wrk( env, e );
5557 static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e )
5559 IRType ty = typeOfIRExpr(env->type_env,e);
5564 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
5569 HReg res = newVRegF(env);
5571 am = iselIntExpr_AModeV(env, e->Iex.Load.addr);
5572 addInstr(env, ARMInstr_VLdStS(True/*isLoad*/, res, am));
5580 HReg res = newVRegF(env);
5581 addInstr(env, ARMInstr_VLdStS(True/*isLoad*/, res, am));
5588 HReg dst = newVRegF(env);
5589 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
5590 addInstr(env, ARMInstr_VXferS(True/*toS*/, dst, src));
5594 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
5595 HReg dst = newVRegF(env);
5596 addInstr(env, ARMInstr_VUnaryS(ARMvfpu_NEG, dst, src));
5600 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
5601 HReg dst = newVRegF(env);
5602 addInstr(env, ARMInstr_VUnaryS(ARMvfpu_ABS, dst, src));
5614 HReg src = iselFltExpr(env, e->Iex.Binop.arg2);
5615 HReg dst = newVRegF(env);
5616 addInstr(env, ARMInstr_VUnaryS(ARMvfpu_SQRT, dst, src));
5620 HReg valD = iselDblExpr(env, e->Iex.Binop.arg2);
5621 set_VFP_rounding_mode(env, e->Iex.Binop.arg1);
5622 HReg valS = newVRegF(env);
5624 addInstr(env, ARMInstr_VCvtSD(False/*!sToD*/, valS, valD));
5625 set_VFP_rounding_default(env);
5642 HReg argL = iselFltExpr(env, triop->arg2);
5643 HReg argR = iselFltExpr(env, triop->arg3);
5644 HReg dst = newVRegF(env);
5652 addInstr(env, ARMInstr_VAluS(op, dst, argL, argR));
5662 && typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1) {
5664 HReg r1 = iselFltExpr(env, e->Iex.ITE.iftrue);
5665 HReg r0 = iselFltExpr(env, e->Iex.ITE.iffalse);
5666 HReg dst = newVRegF(env);
5667 addInstr(env, ARMInstr_VUnaryS(ARMvfpu_COPY, dst, r1));
5668 cc = iselCondCode(env, e->Iex.ITE.cond);
5669 addInstr(env, ARMInstr_VCMovS(cc ^ 1, dst, r0));
5683 static void iselStmt ( ISelEnv* env, IRStmt* stmt )
5695 IRType tya = typeOfIRExpr(env->type_env, stmt->Ist.Store.addr);
5696 IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data);
5703 HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data);
5704 ARMAMode1* am = iselIntExpr_AMode1(env, stmt->Ist.Store.addr);
5705 addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!isLoad*/, rD, am));
5709 HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data);
5710 ARMAMode2* am = iselIntExpr_AMode2(env, stmt->Ist.Store.addr);
5711 addInstr(env, ARMInstr_LdSt16(ARMcc_AL,
5717 HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data);
5718 ARMAMode1* am = iselIntExpr_AMode1(env, stmt->Ist.Store.addr);
5719 addInstr(env, ARMInstr_LdSt8U(ARMcc_AL, False/*!isLoad*/, rD, am));
5723 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
5724 HReg dD = iselNeon64Expr(env, stmt->Ist.Store.data);
5725 ARMAModeN* am = iselIntExpr_AModeN(env, stmt->Ist.Store.addr);
5726 addInstr(env, ARMInstr_NLdStD(False, dD, am));
5729 iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Store.data);
5730 rA = iselIntExpr_R(env, stmt->Ist.Store.addr);
5731 addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!load*/, rDhi,
5733 addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!load*/, rDlo,
5739 HReg dD = iselDblExpr(env, stmt->Ist.Store.data);
5740 ARMAModeV* am = iselIntExpr_AModeV(env, stmt->Ist.Store.addr);
5741 addInstr(env, ARMInstr_VLdStD(False/*!isLoad*/, dD, am));
5745 HReg fD = iselFltExpr(env, stmt->Ist.Store.data);
5746 ARMAModeV* am = iselIntExpr_AModeV(env, stmt->Ist.Store.addr);
5747 addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, fD, am));
5751 HReg qD = iselNeonExpr(env, stmt->Ist.Store.data);
5752 ARMAModeN* am = iselIntExpr_AModeN(env, stmt->Ist.Store.addr);
5753 addInstr(env, ARMInstr_NLdStQ(False, qD, am));
5764 IRType tya = typeOfIRExpr(env->type_env, sg->addr);
5765 IRType tyd = typeOfIRExpr(env->type_env, sg->data);
5774 HReg rD = iselIntExpr_R(env, sg->data);
5775 ARMAMode1* am = iselIntExpr_AMode1(env, sg->addr);
5776 ARMCondCode cc = iselCondCode(env, sg->guard);
5777 addInstr(env, (tyd == Ity_I32 ? ARMInstr_LdSt32 : ARMInstr_LdSt8U)
5782 HReg rD = iselIntExpr_R(env, sg->data);
5783 ARMAMode2* am = iselIntExpr_AMode2(env, sg->addr);
5784 ARMCondCode cc = iselCondCode(env, sg->guard);
5785 addInstr(env, ARMInstr_LdSt16(cc,
5800 IRType tya = typeOfIRExpr(env->type_env, lg->addr);
5809 HReg rAlt = iselIntExpr_R(env, lg->alt);
5810 ARMAMode1* am = iselIntExpr_AMode1(env, lg->addr);
5811 HReg rD = lookupIRTemp(env, lg->dst);
5812 addInstr(env, mk_iMOVds_RR(rD, rAlt));
5813 ARMCondCode cc = iselCondCode(env, lg->guard);
5814 addInstr(env, (lg->cvt == ILGop_Ident32 ? ARMInstr_LdSt32
5822 HReg rAlt = iselIntExpr_R(env, lg->alt);
5823 ARMAMode2* am = iselIntExpr_AMode2(env, lg->addr);
5824 HReg rD = lookupIRTemp(env, lg->dst);
5825 addInstr(env, mk_iMOVds_RR(rD, rAlt));
5826 ARMCondCode cc = iselCondCode(env, lg->guard);
5828 addInstr(env, ARMInstr_Ld8S(cc, rD, am));
5832 addInstr(env, ARMInstr_LdSt16(cc, True/*isLoad*/, sx, rD, am));
5845 IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Put.data);
5848 HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data);
5850 addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!isLoad*/, rD, am));
5854 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
5855 HReg addr = newVRegI(env);
5856 HReg qD = iselNeon64Expr(env, stmt->Ist.Put.data);
5857 addInstr(env, ARMInstr_Add32(addr, hregARM_R8(),
5859 env, ARMInstr_NLdStD(False, qD, mkARMAModeN_R(addr)));
5866 iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Put.data);
5867 addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!isLoad*/,
5869 addInstr(env, ARMInstr_LdSt32(ARMcc_AL, False/*!isLoad*/,
5878 HReg rD = iselDblExpr(env, stmt->Ist.Put.data);
5879 addInstr(env, ARMInstr_VLdStD(False/*!isLoad*/, rD, am));
5886 HReg rD = iselFltExpr(env, stmt->Ist.Put.data);
5887 addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, rD, am));
5891 HReg addr = newVRegI(env);
5892 HReg qD = iselNeonExpr(env, stmt->Ist.Put.data);
5893 addInstr(env, ARMInstr_Add32(addr, hregARM_R8(),
5895 addInstr(env, ARMInstr_NLdStQ(False, qD, mkARMAModeN_R(addr)));
5905 IRType ty = typeOfIRTemp(env->type_env, tmp);
5909 env, stmt->Ist.WrTmp.data);
5910 HReg dst = lookupIRTemp(env, tmp);
5911 addInstr(env, ARMInstr_Mov(dst,ri84));
5922 HReg dst = lookupIRTemp(env, tmp);
5923 ARMCondCode cond = iselCondCode(env, stmt->Ist.WrTmp.data);
5924 addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0)));
5925 addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0)));
5929 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
5930 HReg src = iselNeon64Expr(env, stmt->Ist.WrTmp.data);
5931 HReg dst = lookupIRTemp(env, tmp);
5932 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, dst, src, 4, False));
5935 iselInt64Expr(&rHi,&rLo, env, stmt->Ist.WrTmp.data);
5936 lookupIRTemp64( &dstHi, &dstLo, env, tmp);
5937 addInstr(env, mk_iMOVds_RR(dstHi, rHi) );
5938 addInstr(env, mk_iMOVds_RR(dstLo, rLo) );
5943 HReg src = iselDblExpr(env, stmt->Ist.WrTmp.data);
5944 HReg dst = lookupIRTemp(env, tmp);
5945 addInstr(env, ARMInstr_VUnaryD(ARMvfpu_COPY, dst, src));
5949 HReg src = iselFltExpr(env, stmt->Ist.WrTmp.data);
5950 HReg dst = lookupIRTemp(env, tmp);
5951 addInstr(env, ARMInstr_VUnaryS(ARMvfpu_COPY, dst, src));
5955 HReg src = iselNeonExpr(env, stmt->Ist.WrTmp.data);
5956 HReg dst = lookupIRTemp(env, tmp);
5957 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, dst, src, 4, True));
5971 retty = typeOfIRTemp(env->type_env, d->tmp);
5990 doHelperCall( &addToSp, &rloc, env, d->guard, d->cee, retty, d->args );
6005 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
6006 HReg tmp = lookupIRTemp(env, d->tmp);
6007 addInstr(env, ARMInstr_VXferD(True, tmp, hregARM_R1(),
6013 lookupIRTemp64( &dstHi, &dstLo, env, d->tmp);
6014 addInstr(env, mk_iMOVds_RR(dstHi, hregARM_R1()) );
6015 addInstr(env, mk_iMOVds_RR(dstLo, hregARM_R0()) );
6024 HReg dst = lookupIRTemp(env, d->tmp);
6025 addInstr(env, mk_iMOVds_RR(dst, hregARM_R0()) );
6042 HReg dst = lookupIRTemp(env, d->tmp);
6043 HReg tmp = newVRegI(env);
6045 addInstr(env, ARMInstr_Alu(ARMalu_ADD,
6048 addInstr(env, ARMInstr_NLdStQ(True/*load*/, dst, am));
6049 addInstr(env, ARMInstr_Alu(ARMalu_ADD,
6065 IRType ty = typeOfIRTemp(env->type_env, res);
6068 HReg r_dst = lookupIRTemp(env, res);
6069 HReg raddr = iselIntExpr_R(env, stmt->Ist.LLSC.addr);
6076 addInstr(env, mk_iMOVds_RR(hregARM_R4(), raddr));
6077 addInstr(env, ARMInstr_LdrEX(szB));
6078 addInstr(env, mk_iMOVds_RR(r_dst, hregARM_R2()));
6082 HReg raddr = iselIntExpr_R(env, stmt->Ist.LLSC.addr);
6083 addInstr(env, mk_iMOVds_RR(hregARM_R4(), raddr));
6084 addInstr(env, ARMInstr_LdrEX(8));
6089 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
6090 HReg dst = lookupIRTemp(env, res);
6091 addInstr(env, ARMInstr_VXferD(True, dst, hregARM_R3(),
6095 lookupIRTemp64(&r_dst_hi, &r_dst_lo, env, res);
6096 addInstr(env, mk_iMOVds_RR(r_dst_lo, hregARM_R2()));
6097 addInstr(env, mk_iMOVds_RR(r_dst_hi, hregARM_R3()));
6105 IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.LLSC.storedata);
6108 HReg rD = iselIntExpr_R(env, stmt->Ist.LLSC.storedata);
6109 HReg rA = iselIntExpr_R(env, stmt->Ist.LLSC.addr);
6116 addInstr(env, mk_iMOVds_RR(hregARM_R2(), rD));
6117 addInstr(env, mk_iMOVds_RR(hregARM_R4(), rA));
6118 addInstr(env, ARMInstr_StrEX(szB));
6127 iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.LLSC.storedata);
6128 HReg rA = iselIntExpr_R(env, stmt->Ist.LLSC.addr);
6129 addInstr(env, mk_iMOVds_RR(hregARM_R2(), rDlo));
6130 addInstr(env, mk_iMOVds_RR(hregARM_R3(), rDhi));
6131 addInstr(env, mk_iMOVds_RR(hregARM_R4(), rA));
6132 addInstr(env, ARMInstr_StrEX(8));
6138 IRType ty = typeOfIRTemp(env->type_env, res);
6139 HReg r_res = lookupIRTemp(env, res);
6142 addInstr(env, ARMInstr_Alu(ARMalu_XOR, r_res, hregARM_R0(), one));
6144 addInstr(env, ARMInstr_Alu(ARMalu_AND, r_res, r_res, one));
6154 addInstr(env, ARMInstr_MFence());
6157 addInstr(env, ARMInstr_CLREX());
6178 ARMCondCode cc = iselCondCode(env, stmt->Ist.Exit.guard);
6186 if (env->chainingAllowed) {
6191 = stmt->Ist.Exit.dst->Ico.U32 > env->max_ga;
6193 addInstr(env, ARMInstr_XDirect(stmt->Ist.Exit.dst->Ico.U32,
6199 HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
6200 addInstr(env, ARMInstr_XAssisted(r, amR15T, cc, Ijk_Boring));
6215 HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
6216 addInstr(env, ARMInstr_XAssisted(r, amR15T, cc,
6240 static void iselNext ( ISelEnv* env,
6258 if (env->chainingAllowed) {
6263 = cdst->Ico.U32 > env->max_ga;
6265 addInstr(env, ARMInstr_XDirect(cdst->Ico.U32,
6272 HReg r = iselIntExpr_R(env, next);
6273 addInstr(env, ARMInstr_XAssisted(r, amR15T, ARMcc_AL,
6283 HReg r = iselIntExpr_R(env, next);
6285 if (env->chainingAllowed) {
6286 addInstr(env, ARMInstr_XIndir(r, amR15T, ARMcc_AL));
6288 addInstr(env, ARMInstr_XAssisted(r, amR15T, ARMcc_AL,
6307 HReg r = iselIntExpr_R(env, next);
6309 addInstr(env, ARMInstr_XAssisted(r, amR15T, ARMcc_AL, jk));
6343 ISelEnv* env;
6360 env = LibVEX_Alloc_inline(sizeof(ISelEnv));
6361 env->vreg_ctr = 0;
6364 env->code = newHInstrArray();
6366 /* Copy BB's type env. */
6367 env->type_env = bb->tyenv;
6371 env->n_vregmap = bb->tyenv->types_used;
6372 env->vregmap = LibVEX_Alloc_inline(env->n_vregmap * sizeof(HReg));
6373 env->vregmapHI = LibVEX_Alloc_inline(env->n_vregmap * sizeof(HReg));
6376 env->chainingAllowed = chainingAllowed;
6377 env->hwcaps = hwcaps_host;
6378 env->max_ga = max_ga;
6383 for (i = 0; i < env->n_vregmap; i++) {
6404 env->vregmap[i] = hreg;
6405 env->vregmapHI[i] = hregHI;
6407 env->vreg_ctr = j;
6412 addInstr(env, ARMInstr_EvCheck(amCounter, amFailAddr));
6419 addInstr(env, ARMInstr_ProfInc());
6424 iselStmt(env, bb->stmts[i]);
6426 iselNext(env, bb->next, bb->jumpkind, bb->offsIP);
6429 env->code->n_vregs = env->vreg_ctr;
6430 return env->code;
