Lines Matching refs:mode64
48 const RRegUniverse* getRRegUniverse_MIPS ( Bool mode64 )
60 UInt howNeeded = mode64 ? 2 : 1;
69 ru->regs[ru->size++] = hregMIPS_GPR16(mode64);
70 ru->regs[ru->size++] = hregMIPS_GPR17(mode64);
71 ru->regs[ru->size++] = hregMIPS_GPR18(mode64);
72 ru->regs[ru->size++] = hregMIPS_GPR19(mode64);
73 ru->regs[ru->size++] = hregMIPS_GPR20(mode64);
74 ru->regs[ru->size++] = hregMIPS_GPR21(mode64);
75 ru->regs[ru->size++] = hregMIPS_GPR22(mode64);
77 ru->regs[ru->size++] = hregMIPS_GPR12(mode64);
78 ru->regs[ru->size++] = hregMIPS_GPR13(mode64);
79 ru->regs[ru->size++] = hregMIPS_GPR14(mode64);
80 ru->regs[ru->size++] = hregMIPS_GPR15(mode64);
81 ru->regs[ru->size++] = hregMIPS_GPR24(mode64);
83 ru->regs[ru->size++] = hregMIPS_F16(mode64);
84 ru->regs[ru->size++] = hregMIPS_F18(mode64);
85 ru->regs[ru->size++] = hregMIPS_F20(mode64);
86 ru->regs[ru->size++] = hregMIPS_F22(mode64);
87 ru->regs[ru->size++] = hregMIPS_F24(mode64);
88 ru->regs[ru->size++] = hregMIPS_F26(mode64);
89 ru->regs[ru->size++] = hregMIPS_F28(mode64);
90 ru->regs[ru->size++] = hregMIPS_F30(mode64);
91 if (!mode64) {
93 ru->regs[ru->size++] = hregMIPS_D0(mode64);
94 ru->regs[ru->size++] = hregMIPS_D1(mode64);
95 ru->regs[ru->size++] = hregMIPS_D2(mode64);
96 ru->regs[ru->size++] = hregMIPS_D3(mode64);
97 ru->regs[ru->size++] = hregMIPS_D4(mode64);
98 ru->regs[ru->size++] = hregMIPS_D5(mode64);
99 ru->regs[ru->size++] = hregMIPS_D6(mode64);
100 ru->regs[ru->size++] = hregMIPS_D7(mode64);
106 ru->regs[ru->size++] = hregMIPS_HI(mode64);
107 ru->regs[ru->size++] = hregMIPS_LO(mode64);
108 ru->regs[ru->size++] = hregMIPS_GPR0(mode64);
109 ru->regs[ru->size++] = hregMIPS_GPR1(mode64);
110 ru->regs[ru->size++] = hregMIPS_GPR2(mode64);
111 ru->regs[ru->size++] = hregMIPS_GPR3(mode64);
112 ru->regs[ru->size++] = hregMIPS_GPR4(mode64);
113 ru->regs[ru->size++] = hregMIPS_GPR5(mode64);
114 ru->regs[ru->size++] = hregMIPS_GPR6(mode64);
115 ru->regs[ru->size++] = hregMIPS_GPR7(mode64);
116 ru->regs[ru->size++] = hregMIPS_GPR8(mode64);
117 ru->regs[ru->size++] = hregMIPS_GPR9(mode64);
118 ru->regs[ru->size++] = hregMIPS_GPR10(mode64);
119 ru->regs[ru->size++] = hregMIPS_GPR11(mode64);
120 ru->regs[ru->size++] = hregMIPS_GPR23(mode64);
121 ru->regs[ru->size++] = hregMIPS_GPR25(mode64);
122 ru->regs[ru->size++] = hregMIPS_GPR29(mode64);
123 ru->regs[ru->size++] = hregMIPS_GPR31(mode64);
132 void ppHRegMIPS(HReg reg, Bool mode64)
527 void ppMIPSAMode(MIPSAMode * am, Bool mode64)
535 ppHRegMIPS(am->Mam.IR.base, mode64);
539 ppHRegMIPS(am->Mam.RR.base, mode64);
541 ppHRegMIPS(am->Mam.RR.index, mode64);
605 void ppMIPSRH(MIPSRH * op, Bool mode64)
616 ppHRegMIPS(op->Mrh.Reg.reg, mode64);
938 MIPSInstr *MIPSInstr_Load(UChar sz, HReg dst, MIPSAMode * src, Bool mode64)
948 vassert(mode64);
952 MIPSInstr *MIPSInstr_Store(UChar sz, MIPSAMode * dst, HReg src, Bool mode64)
962 vassert(mode64);
966 MIPSInstr *MIPSInstr_LoadL(UChar sz, HReg dst, MIPSAMode * src, Bool mode64)
976 vassert(mode64);
981 HReg expd, HReg data, Bool mode64)
993 vassert(mode64);
997 MIPSInstr *MIPSInstr_StoreC(UChar sz, MIPSAMode * dst, HReg src, Bool mode64)
1007 vassert(mode64);
1175 static void ppLoadImm(HReg dst, ULong imm, Bool mode64)
1178 ppHRegMIPS(dst, mode64);
1182 void ppMIPSInstr(const MIPSInstr * i, Bool mode64)
1186 ppLoadImm(i->Min.LI.dst, i->Min.LI.imm, mode64);
1194 ppHRegMIPS(i->Min.Alu.dst, mode64);
1196 ppHRegMIPS(r_srcL, mode64);
1198 ppMIPSRH(rh_srcR, mode64);
1207 ppHRegMIPS(i->Min.Shft.dst, mode64);
1209 ppHRegMIPS(r_srcL, mode64);
1211 ppMIPSRH(rh_srcR, mode64);
1216 ppHRegMIPS(i->Min.Unary.dst, mode64);
1218 ppHRegMIPS(i->Min.Unary.src, mode64);
1223 ppHRegMIPS(i->Min.Cmp.dst, mode64);
1225 ppHRegMIPS(i->Min.Cmp.srcL, mode64);
1227 ppHRegMIPS(i->Min.Cmp.srcR, mode64);
1236 ppHRegMIPS(i->Min.Mul.dst, mode64);
1238 ppHRegMIPS(i->Min.Mul.srcL, mode64);
1240 ppHRegMIPS(i->Min.Mul.srcR, mode64);
1245 ppHRegMIPS(i->Min.Mul.dst, mode64);
1247 ppHRegMIPS(i->Min.Mul.srcL, mode64);
1249 ppHRegMIPS(i->Min.Mul.srcR, mode64);
1256 ppHRegMIPS(i->Min.MtHL.src, mode64);
1261 ppHRegMIPS(i->Min.MtHL.src, mode64);
1266 ppHRegMIPS(i->Min.MfHL.dst, mode64);
1271 ppHRegMIPS(i->Min.MfHL.dst, mode64);
1276 ppHRegMIPS(i->Min.Macc.srcL, mode64);
1278 ppHRegMIPS(i->Min.Macc.srcR, mode64);
1286 ppHRegMIPS(i->Min.Div.srcL, mode64);
1288 ppHRegMIPS(i->Min.Div.srcR, mode64);
1298 if (!mode64)
1301 ppLoadImm(hregMIPS_GPR25(mode64), i->Min.Call.target, mode64);
1312 if (!mode64)
1323 ppMIPSAMode(i->Min.XDirect.amPC, mode64);
1331 ppHRegMIPS(i->Min.XIndir.dstGA, mode64);
1333 ppMIPSAMode(i->Min.XIndir.amPC, mode64);
1341 ppHRegMIPS(i->Min.XAssisted.dstGA, mode64);
1343 ppMIPSAMode(i->Min.XAssisted.amPC, mode64);
1353 ppHRegMIPS(i->Min.Load.dst, mode64);
1355 ppMIPSAMode(i->Min.Load.src, mode64);
1363 ppHRegMIPS(i->Min.Store.src, mode64);
1365 ppMIPSAMode(i->Min.Store.dst, mode64);
1370 ppHRegMIPS(i->Min.LoadL.dst, mode64);
1372 ppMIPSAMode(i->Min.LoadL.src, mode64);
1390 ppHRegMIPS(i->Min.Cas.old , mode64);
1392 ppHRegMIPS(i->Min.Cas.addr , mode64);
1396 ppHRegMIPS(i->Min.Cas.old , mode64);
1398 ppHRegMIPS(i->Min.Cas.expd , mode64);
1404 ppHRegMIPS(i->Min.Cas.old , mode64);
1406 ppHRegMIPS(i->Min.Cas.old , mode64);
1410 ppHRegMIPS(i->Min.Cas.data , mode64);
1412 ppHRegMIPS(i->Min.Cas.addr , mode64);
1416 ppHRegMIPS(i->Min.Cas.old , mode64);
1418 ppHRegMIPS(i->Min.Cas.expd , mode64);
1420 ppHRegMIPS(i->Min.Cas.data , mode64);
1426 ppHRegMIPS(i->Min.StoreC.src, mode64);
1428 ppMIPSAMode(i->Min.StoreC.dst, mode64);
1433 ppHRegMIPS(i->Min.RdWrLR.gpr, mode64);
1438 ppHRegMIPS(i->Min.FpUnary.dst, mode64);
1440 ppHRegMIPS(i->Min.FpUnary.src, mode64);
1444 ppHRegMIPS(i->Min.FpBinary.dst, mode64);
1446 ppHRegMIPS(i->Min.FpBinary.srcL, mode64);
1448 ppHRegMIPS(i->Min.FpBinary.srcR, mode64);
1452 ppHRegMIPS(i->Min.FpTernary.dst, mode64);
1454 ppHRegMIPS(i->Min.FpTernary.src1, mode64);
1456 ppHRegMIPS(i->Min.FpTernary.src2, mode64);
1458 ppHRegMIPS(i->Min.FpTernary.src3, mode64);
1462 ppHRegMIPS(i->Min.FpConvert.dst, mode64);
1464 ppHRegMIPS(i->Min.FpConvert.src, mode64);
1468 ppHRegMIPS(i->Min.FpCompare.srcL, mode64);
1470 ppHRegMIPS(i->Min.FpCompare.srcR, mode64);
1474 ppHRegMIPS(i->Min.FpMulAcc.dst, mode64);
1476 ppHRegMIPS(i->Min.FpMulAcc.srcML, mode64);
1478 ppHRegMIPS(i->Min.FpMulAcc.srcMR, mode64);
1480 ppHRegMIPS(i->Min.FpMulAcc.srcAcc, mode64);
1486 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1488 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1491 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1493 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1498 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1500 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1503 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1505 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1512 ppHRegMIPS(i->Min.MtFCSR.src, mode64);
1518 ppHRegMIPS(i->Min.MfFCSR.dst, mode64);
1524 ppHRegMIPS(i->Min.FpGpMove.dst, mode64);
1526 ppHRegMIPS(i->Min.FpGpMove.src, mode64);
1531 ppHRegMIPS(i->Min.MoveCond.dst, mode64);
1533 ppHRegMIPS(i->Min.MoveCond.src, mode64);
1535 ppHRegMIPS(i->Min.MoveCond.cond, mode64);
1540 ppMIPSAMode(i->Min.EvCheck.amCounter, mode64);
1543 ppMIPSAMode(i->Min.EvCheck.amCounter, mode64);
1545 ppMIPSAMode(i->Min.EvCheck.amFailAddr, mode64);
1549 if (mode64)
1572 void getRegUsage_MIPSInstr(HRegUsage * u, const MIPSInstr * i, Bool mode64)
1605 addHRegUse(u, HRmWrite, hregMIPS_HI(mode64));
1606 addHRegUse(u, HRmWrite, hregMIPS_LO(mode64));
1611 addHRegUse(u, HRmRead, hregMIPS_HI(mode64));
1612 addHRegUse(u, HRmRead, hregMIPS_LO(mode64));
1622 addHRegUse(u, HRmModify, hregMIPS_HI(mode64));
1623 addHRegUse(u, HRmModify, hregMIPS_LO(mode64));
1628 addHRegUse(u, HRmWrite, hregMIPS_HI(mode64));
1629 addHRegUse(u, HRmWrite, hregMIPS_LO(mode64));
1640 addHRegUse(u, HRmWrite, hregMIPS_GPR1(mode64));
1642 addHRegUse(u, HRmWrite, hregMIPS_GPR2(mode64));
1643 addHRegUse(u, HRmWrite, hregMIPS_GPR3(mode64));
1645 addHRegUse(u, HRmWrite, hregMIPS_GPR4(mode64));
1646 addHRegUse(u, HRmWrite, hregMIPS_GPR5(mode64));
1647 addHRegUse(u, HRmWrite, hregMIPS_GPR6(mode64));
1648 addHRegUse(u, HRmWrite, hregMIPS_GPR7(mode64));
1650 addHRegUse(u, HRmWrite, hregMIPS_GPR8(mode64));
1651 addHRegUse(u, HRmWrite, hregMIPS_GPR9(mode64));
1652 addHRegUse(u, HRmWrite, hregMIPS_GPR10(mode64));
1653 addHRegUse(u, HRmWrite, hregMIPS_GPR11(mode64));
1654 addHRegUse(u, HRmWrite, hregMIPS_GPR12(mode64));
1655 addHRegUse(u, HRmWrite, hregMIPS_GPR13(mode64));
1656 addHRegUse(u, HRmWrite, hregMIPS_GPR14(mode64));
1657 addHRegUse(u, HRmWrite, hregMIPS_GPR15(mode64));
1659 addHRegUse(u, HRmWrite, hregMIPS_GPR24(mode64));
1660 addHRegUse(u, HRmWrite, hregMIPS_GPR25(mode64));
1661 addHRegUse(u, HRmWrite, hregMIPS_GPR31(mode64));
1666 if (argir & (1<<11)) addHRegUse(u, HRmRead, hregMIPS_GPR11(mode64));
1667 if (argir & (1<<10)) addHRegUse(u, HRmRead, hregMIPS_GPR10(mode64));
1668 if (argir & (1<<9)) addHRegUse(u, HRmRead, hregMIPS_GPR9(mode64));
1669 if (argir & (1<<8)) addHRegUse(u, HRmRead, hregMIPS_GPR8(mode64));
1670 if (argir & (1<<7)) addHRegUse(u, HRmRead, hregMIPS_GPR7(mode64));
1671 if (argir & (1<<6)) addHRegUse(u, HRmRead, hregMIPS_GPR6(mode64));
1672 if (argir & (1<<5)) addHRegUse(u, HRmRead, hregMIPS_GPR5(mode64));
1673 if (argir & (1<<4)) addHRegUse(u, HRmRead, hregMIPS_GPR4(mode64));
1780 ppMIPSInstr(i, mode64);
1792 void mapRegs_MIPSInstr(HRegRemap * m, MIPSInstr * i, Bool mode64)
1940 ppMIPSInstr(i, mode64);
1972 Int offsetB, Bool mode64)
1978 am = MIPSAMode_IR(offsetB, GuestStatePointer(mode64));
1982 vassert(mode64);
1983 *i1 = MIPSInstr_Store(8, am, rreg, mode64);
1986 vassert(!mode64);
1987 *i1 = MIPSInstr_Store(4, am, rreg, mode64);
1990 vassert(!mode64);
2004 Int offsetB, Bool mode64)
2008 am = MIPSAMode_IR(offsetB, GuestStatePointer(mode64));
2012 vassert(mode64);
2013 *i1 = MIPSInstr_Load(8, rreg, am, mode64);
2016 vassert(!mode64);
2017 *i1 = MIPSInstr_Load(4, rreg, am, mode64);
2020 if (mode64)
2037 inline static UInt iregNo(HReg r, Bool mode64)
2040 vassert(hregClass(r) == (mode64 ? HRcInt64 : HRcInt32));
2047 inline static UInt fregNo(HReg r, Bool mode64)
2170 Bool mode64)
2176 rA = iregNo(am->Mam.IR.base, mode64);
2210 Bool mode64)
2215 rA = iregNo(am->Mam.RR.base, mode64);
2216 rB = iregNo(am->Mam.RR.index, mode64);
2233 if (mode64) {
2262 static UChar *mkLoadImm(UChar * p, UInt r_dst, ULong imm, Bool mode64)
2264 if (!mode64) {
2285 vassert(mode64);
2308 UInt r_dst, ULong imm, Bool mode64)
2312 if (!mode64) {
2321 if (!mode64) {
2330 vassert(mode64);
2350 UInt r_dst, ULong imm, Bool mode64 )
2354 if (!mode64) {
2363 if (!mode64) {
2407 MIPSAMode* am, Bool mode64 )
2412 if (mode64) {
2415 p = doAMode_IR(p, mode64 ? 55 : 35, reg, am, mode64);
2429 if (mode64) {
2432 p = doAMode_IR(p, mode64 ? 63 : 43, reg, am, mode64);
2450 MIPSAMode* am, Bool mode64 )
2455 if (mode64) {
2458 p = doAMode_IR(p, 35, reg, am, mode64);
2472 if (mode64) {
2475 p = doAMode_IR(p, 43, reg, am, mode64);
2510 Bool mode64,
2523 p = mkLoadImm(p, iregNo(i->Min.LI.dst, mode64), i->Min.LI.imm, mode64);
2529 UInt r_dst = iregNo(i->Min.Alu.dst, mode64);
2530 UInt r_srcL = iregNo(i->Min.Alu.srcL, mode64);
2532 mode64);
2642 UInt r_dst = iregNo(i->Min.Shft.dst, mode64);
2643 UInt r_srcL = iregNo(i->Min.Shft.srcL, mode64);
2645 mode64);
2646 if (!mode64)
2736 UInt r_dst = iregNo(i->Min.Unary.dst, mode64);
2737 UInt r_src = iregNo(i->Min.Unary.src, mode64);
2761 UInt r_srcL = iregNo(i->Min.Cmp.srcL, mode64);
2762 UInt r_srcR = iregNo(i->Min.Cmp.srcR, mode64);
2763 UInt r_dst = iregNo(i->Min.Cmp.dst, mode64);
2808 UInt r_srcL = iregNo(i->Min.Mul.srcL, mode64);
2809 UInt r_srcR = iregNo(i->Min.Mul.srcR, mode64);
2810 UInt r_dst = iregNo(i->Min.Mul.dst, mode64);
2829 else if (mode64 && !sz32)
2839 UInt r_srcL = iregNo(i->Min.Macc.srcL, mode64);
2840 UInt r_srcR = iregNo(i->Min.Macc.srcR, mode64);
2879 UInt r_srcL = iregNo(i->Min.Div.srcL, mode64);
2880 UInt r_srcR = iregNo(i->Min.Div.srcR, mode64);
2901 UInt r_src = iregNo(i->Min.MtHL.src, mode64);
2907 UInt r_src = iregNo(i->Min.MtHL.src, mode64);
2913 UInt r_dst = iregNo(i->Min.MfHL.dst, mode64);
2919 UInt r_dst = iregNo(i->Min.MfHL.dst, mode64);
2925 UInt r_src = iregNo(i->Min.MtFCSR.src, mode64);
2932 UInt r_dst = iregNo(i->Min.MfFCSR.dst, mode64);
2963 if (!mode64) {
2969 p = mkLoadImm(p, r_dst, i->Min.Call.target, mode64);
2975 if (!mode64) {
2982 UInt r_src = iregNo(i->Min.Call.src, mode64);
3019 mode64);
3021 i->Min.XDirect.amPC, mode64);
3034 (Addr)disp_cp_chain_me, mode64);
3050 ptmp = mkFormI(ptmp, 35, GuestSP, 9, COND_OFFSET(mode64));
3080 iregNo(i->Min.XIndir.dstGA, mode64),
3081 i->Min.XIndir.amPC, mode64);
3087 (Addr)disp_cp_xindir, mode64);
3100 ptmp = mkFormI(ptmp, 35, GuestSP, 9, COND_OFFSET(mode64));
3121 iregNo(i->Min.XIndir.dstGA, mode64),
3122 i->Min.XIndir.amPC, mode64);
3153 p = mkLoadImm_EXACTLY2or6(p, /*r*/ GuestSP, trcval, mode64);
3157 (ULong)(Addr)disp_cp_xassisted, mode64);
3172 ptmp = mkFormI(ptmp, 35, GuestSP, 9, COND_OFFSET(mode64));
3182 UInt r_dst = iregNo(i->Min.Load.dst, mode64);
3184 if (mode64 && (sz == 4 || sz == 8)) {
3200 vassert(mode64);
3206 p = doAMode_IR(p, opc, r_dst, am_addr, mode64);
3209 UInt r_dst = iregNo(i->Min.Load.dst, mode64);
3224 vassert(mode64);
3230 p = doAMode_RR(p, opc, r_dst, am_addr, mode64);
3239 UInt r_src = iregNo(i->Min.Store.src, mode64);
3241 if (mode64 && (sz == 4 || sz == 8)) {
3256 vassert(mode64);
3263 p = doAMode_IR(p, opc, r_src, am_addr, mode64);
3266 UInt r_src = iregNo(i->Min.Store.src, mode64);
3280 vassert(mode64);
3287 p = doAMode_RR(p, opc, r_src, am_addr, mode64);
3294 UInt r_src = iregNo(am_addr->Mam.IR.base, mode64);
3296 UInt r_dst = iregNo(i->Min.LoadL.dst, mode64);
3306 UInt r_src = iregNo(i->Min.StoreC.src, mode64);
3308 UInt r_dst = iregNo(am_addr->Mam.IR.base, mode64);
3319 UInt old = iregNo(i->Min.Cas.old, mode64);
3320 UInt addr = iregNo(i->Min.Cas.addr, mode64);
3321 UInt expd = iregNo(i->Min.Cas.expd, mode64);
3322 UInt data = iregNo(i->Min.Cas.data, mode64);
3350 UInt reg = iregNo(i->Min.RdWrLR.gpr, mode64);
3365 UInt f_reg = fregNo(i->Min.FpLdSt.reg, mode64);
3368 p = doAMode_IR(p, 0x31, f_reg, am_addr, mode64);
3370 p = doAMode_RR(p, 0x31, f_reg, am_addr, mode64);
3373 p = doAMode_IR(p, 0x39, f_reg, am_addr, mode64);
3375 p = doAMode_RR(p, 0x39, f_reg, am_addr, mode64);
3381 p = doAMode_IR(p, 0x35, f_reg, am_addr, mode64);
3383 p = doAMode_RR(p, 0x35, f_reg, am_addr, mode64);
3387 p = doAMode_IR(p, 0x3d, f_reg, am_addr, mode64);
3389 p = doAMode_RR(p, 0x3d, f_reg, am_addr, mode64);
3399 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3400 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3411 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3412 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3423 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3424 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3435 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3436 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3455 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3456 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3457 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3462 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3463 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3464 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3469 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3470 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3471 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3476 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3477 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3478 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3519 UInt fr_dst = fregNo(i->Min.FpTernary.dst, mode64);
3520 UInt fr_src1 = fregNo(i->Min.FpTernary.src1, mode64);
3521 UInt fr_src2 = fregNo(i->Min.FpTernary.src2, mode64);
3522 UInt fr_src3 = fregNo(i->Min.FpTernary.src3, mode64);
3535 UInt fr_dst = fregNo(i->Min.FpTernary.dst, mode64);
3536 UInt fr_src1 = fregNo(i->Min.FpTernary.src1, mode64);
3537 UInt fr_src2 = fregNo(i->Min.FpTernary.src2, mode64);
3538 UInt fr_src3 = fregNo(i->Min.FpTernary.src3, mode64);
3560 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3565 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3566 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3570 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3575 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3576 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3581 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3591 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3596 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3600 if (mode64) {
3601 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3605 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3615 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3616 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3620 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3625 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3635 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3636 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3640 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3646 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3655 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3656 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3660 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3670 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3671 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3675 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3692 UInt r_dst = iregNo(i->Min.FpCompare.dst, mode64);
3728 rt = iregNo(i->Min.FpGpMove.dst, mode64);
3729 fs = fregNo(i->Min.FpGpMove.src, mode64);
3734 vassert(mode64);
3735 rt = iregNo(i->Min.FpGpMove.dst, mode64);
3736 fs = fregNo(i->Min.FpGpMove.src, mode64);
3741 rt = iregNo(i->Min.FpGpMove.src, mode64);
3742 fs = fregNo(i->Min.FpGpMove.dst, mode64);
3747 vassert(mode64);
3748 rt = iregNo(i->Min.FpGpMove.src, mode64);
3749 fs = fregNo(i->Min.FpGpMove.dst, mode64);
3763 d = fregNo(i->Min.MoveCond.dst, mode64);
3764 s = fregNo(i->Min.MoveCond.src, mode64);
3765 t = iregNo(i->Min.MoveCond.cond, mode64);
3772 t = iregNo(i->Min.MoveCond.cond, mode64);
3777 d = iregNo(i->Min.MoveCond.dst, mode64);
3778 s = iregNo(i->Min.MoveCond.src, mode64);
3779 t = iregNo(i->Min.MoveCond.cond, mode64);
3804 i->Min.EvCheck.amCounter, mode64);
3809 i->Min.EvCheck.amCounter, mode64);
3814 i->Min.EvCheck.amFailAddr, mode64);
3830 if (mode64) {
3839 True /*mode64*/);
3861 False /*!mode64*/);
3897 ppMIPSInstr(i, mode64);
3919 Bool mode64 )
3935 mode64));
3936 vassert(fetch32(p + (mode64 ? 24 : 8) + 0) == 0x120F809);
3937 vassert(fetch32(p + (mode64 ? 24 : 8) + 4) == 0x00000000);
3951 (Addr)place_to_jump_to, mode64);
3956 vassert(len == (mode64 ? 32 : 16)); /* stay sane */
3967 Bool mode64 )
3983 mode64));
3984 vassert(fetch32(p + (mode64 ? 24 : 8) + 0) == 0x120F809);
3985 vassert(fetch32(p + (mode64 ? 24 : 8) + 4) == 0x00000000);
3997 (Addr)disp_cp_chain_me, mode64);
4002 vassert(len == (mode64 ? 32 : 16)); /* stay sane */
4012 Bool mode64 )
4015 if (mode64) {
4023 mode64 ? 0x6555655565556555ULL : 0x65556555,
4024 mode64));
4026 if (mode64) {
4041 (Addr)location_of_counter, mode64);
