Lines Matching defs:env
133 static HReg lookupIRTemp(ISelEnv * env, IRTemp tmp)
136 vassert(tmp < env->n_vregmap);
137 return env->vregmap[tmp];
140 static void lookupIRTemp64(HReg * vrHI, HReg * vrLO, ISelEnv * env, IRTemp tmp)
143 vassert(tmp < env->n_vregmap);
144 vassert(! hregIsInvalid(env->vregmapHI[tmp]));
145 *vrLO = env->vregmap[tmp];
146 *vrHI = env->vregmapHI[tmp];
150 lookupIRTempPair(HReg * vrHI, HReg * vrLO, ISelEnv * env, IRTemp tmp)
152 vassert(env->mode64);
154 vassert(tmp < env->n_vregmap);
155 vassert(! hregIsInvalid(env->vregmapHI[tmp]));
156 *vrLO = env->vregmap[tmp];
157 *vrHI = env->vregmapHI[tmp];
160 static void addInstr(ISelEnv * env, MIPSInstr * instr)
162 addHInstr(env->code, instr);
169 static HReg newVRegI(ISelEnv * env)
172 HRcGPR(env->mode64), 0/*enc*/, env->vreg_ctr);
173 env->vreg_ctr++;
177 static HReg newVRegD(ISelEnv * env)
180 HRcFlt64, 0/*enc*/, env->vreg_ctr);
181 env->vreg_ctr++;
185 static HReg newVRegF(ISelEnv * env)
188 HRcFPR(env->mode64), 0/*enc*/, env->vreg_ctr);
189 env->vreg_ctr++;
193 static void add_to_sp(ISelEnv * env, UInt n)
198 addInstr(env, MIPSInstr_Alu(Malu_DADD, sp, sp, MIPSRH_Imm(True,
201 addInstr(env, MIPSInstr_Alu(Malu_ADD, sp, sp, MIPSRH_Imm(True,
205 static void sub_from_sp(ISelEnv * env, UInt n)
210 addInstr(env, MIPSInstr_Alu(Malu_DSUB, sp, sp,
213 addInstr(env, MIPSInstr_Alu(Malu_SUB, sp, sp,
234 static MIPSRH *iselWordExpr_RH_wrk(ISelEnv * env, Bool syned, IRExpr * e);
235 static MIPSRH *iselWordExpr_RH(ISelEnv * env, Bool syned, IRExpr * e);
239 static MIPSRH *iselWordExpr_RH5u_wrk(ISelEnv * env, IRExpr * e);
240 static MIPSRH *iselWordExpr_RH5u(ISelEnv * env, IRExpr * e);
244 static MIPSRH *iselWordExpr_RH6u_wrk(ISelEnv * env, IRExpr * e);
245 static MIPSRH *iselWordExpr_RH6u(ISelEnv * env, IRExpr * e);
248 static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e);
249 static HReg iselWordExpr_R(ISelEnv * env, IRExpr * e);
252 static MIPSAMode *iselWordExpr_AMode_wrk(ISelEnv * env, IRExpr * e,
254 static MIPSAMode *iselWordExpr_AMode(ISelEnv * env, IRExpr * e, IRType xferTy);
256 static void iselInt64Expr_wrk(HReg * rHi, HReg * rLo, ISelEnv * env,
258 static void iselInt64Expr(HReg * rHi, HReg * rLo, ISelEnv * env, IRExpr * e);
262 ISelEnv * env, IRExpr * e);
263 static void iselInt128Expr(HReg * rHi, HReg * rLo, ISelEnv * env, IRExpr * e);
265 static MIPSCondCode iselCondCode_wrk(ISelEnv * env, IRExpr * e);
266 static MIPSCondCode iselCondCode(ISelEnv * env, IRExpr * e);
268 static HReg iselDblExpr_wrk(ISelEnv * env, IRExpr * e);
269 static HReg iselDblExpr(ISelEnv * env, IRExpr * e);
271 static HReg iselFltExpr_wrk(ISelEnv * env, IRExpr * e);
272 static HReg iselFltExpr(ISelEnv * env, IRExpr * e);
274 static void set_MIPS_rounding_mode(ISelEnv * env, IRExpr * mode)
285 HReg irrm = iselWordExpr_R(env, mode);
286 HReg tmp = newVRegI(env);
287 HReg fcsr_old = newVRegI(env);
290 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tmp, irrm,
292 addInstr(env, MIPSInstr_Alu(Malu_XOR, tmp, irrm, MIPSRH_Reg(tmp)));
293 addInstr(env, MIPSInstr_Alu(Malu_AND, irrm, tmp, MIPSRH_Imm(False, 3)));
295 addInstr(env, MIPSInstr_MfFCSR(fcsr_old));
296 sub_from_sp(env, 8); /* Move SP down 8 bytes */
300 addInstr(env, MIPSInstr_Store(4, am_addr, fcsr_old, mode64));
303 addInstr(env, MIPSInstr_MtFCSR(irrm));
306 static void set_MIPS_rounding_default(ISelEnv * env)
308 HReg fcsr = newVRegI(env);
313 addInstr(env, MIPSInstr_Load(4, fcsr, am_addr, mode64));
315 add_to_sp(env, 8); /* Reset SP */
318 addInstr(env, MIPSInstr_MtFCSR(fcsr));
355 static HReg mk_LoadRR32toFPR(ISelEnv * env, HReg r_srcHi, HReg r_srcLo)
357 HReg fr_dst = newVRegD(env);
363 sub_from_sp(env, 16); /* Move SP down 16 bytes */
369 addInstr(env, MIPSInstr_Store(4, am_addr0, r_srcLo, mode64));
370 addInstr(env, MIPSInstr_Store(4, am_addr1, r_srcHi, mode64));
372 addInstr(env, MIPSInstr_Store(4, am_addr0, r_srcHi, mode64));
373 addInstr(env, MIPSInstr_Store(4, am_addr1, r_srcLo, mode64));
381 addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 8, fr_dst, am_addr0));
383 add_to_sp(env, 16); /* Reset SP */
396 ISelEnv* env,
519 aTy = typeOfIRExpr(env->type_env, arg);
523 addInstr(env, mk_iMOVds_RR(argregs[argreg],
524 iselWordExpr_R(env, arg)));
532 iselInt64Expr(&rHi, &rLo, env, arg);
534 addInstr(env, mk_iMOVds_RR( argregs[argreg++], rHi ));
536 addInstr(env, mk_iMOVds_RR( argregs[argreg], rLo));
540 addInstr(env, mk_iMOVds_RR(argregs[argreg],
560 aTy = typeOfIRExpr(env->type_env, arg);
563 tmpregs[argreg] = iselWordExpr_R(env, arg);
571 iselInt64Expr(&raHi, &raLo, env, arg);
596 cc = iselCondCode(env, guard);
597 src = iselWordExpr_R(env, guard);
607 addInstr(env, mk_iMOVds_RR(argregs[i], tmpregs[i]));
650 addInstr(env, MIPSInstr_CallAlways(cc, target, argiregs,
653 addInstr(env, MIPSInstr_Call(cc, target, argiregs, src, *retloc));
688 static Bool sane_AMode(ISelEnv * env, MIPSAMode * am)
705 static MIPSAMode *iselWordExpr_AMode(ISelEnv * env, IRExpr * e, IRType xferTy)
707 MIPSAMode *am = iselWordExpr_AMode_wrk(env, e, xferTy);
708 vassert(sane_AMode(env, am));
713 static MIPSAMode *iselWordExpr_AMode_wrk(ISelEnv * env, IRExpr * e,
716 IRType ty = typeOfIRExpr(env->type_env, e);
717 if (env->mode64) {
729 iselWordExpr_R(env, e->Iex.Binop.arg1));
734 HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1);
735 HReg r_idx = iselWordExpr_R(env, e->Iex.Binop.arg2);
748 iselWordExpr_R(env, e->Iex.Binop.arg1));
753 HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1);
754 HReg r_idx = iselWordExpr_R(env, e->Iex.Binop.arg2);
762 return MIPSAMode_IR(0, iselWordExpr_R(env, e));
783 static HReg iselWordExpr_R(ISelEnv * env, IRExpr * e)
785 HReg r = iselWordExpr_R_wrk(env, e);
788 vassert(hregClass(r) == HRcGPR(env->mode64));
794 static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e)
797 IRType ty = typeOfIRExpr(env->type_env, e);
805 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
809 HReg r_dst = newVRegI(env);
810 MIPSAMode *am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, ty);
816 addInstr(env, MIPSInstr_Load(toUChar(sizeofIRType(ty)),
877 HReg r_dst = newVRegI(env);
878 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
886 ri_srcR = iselWordExpr_RH(env, True /*signed */ ,
892 ri_srcR = iselWordExpr_RH(env, False /*unsigned */,
898 addInstr(env, MIPSInstr_Alu(aluOp, r_dst, r_srcL, ri_srcR));
923 HReg r_dst = newVRegI(env);
924 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
927 ri_srcR = iselWordExpr_RH6u(env, e->Iex.Binop.arg2);
929 ri_srcR = iselWordExpr_RH5u(env, e->Iex.Binop.arg2);
935 HReg tmp = newVRegI(env);
936 HReg r_srcL_se = newVRegI(env);
944 addInstr(env, MIPSInstr_Shft(Mshft_SLL, False, tmp,
946 addInstr(env
949 addInstr(env, MIPSInstr_Shft(shftOp, True /*32bit shift */,
952 addInstr(env, MIPSInstr_Shft(shftOp, True /*32bit shift */,
956 addInstr(env, MIPSInstr_Shft(shftOp, False/*64bit shift */,
984 HReg dst = newVRegI(env);
985 HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1);
986 HReg r2 = iselWordExpr_R(env, e->Iex.Binop.arg2);
1045 addInstr(env, MIPSInstr_Cmp(syned, size32, dst, r1, r2, cc));
1050 HReg tmp = newVRegI(env);
1051 HReg r_dst = newVRegI(env);
1052 HReg argL = iselWordExpr_R(env, e->Iex.Binop.arg1);
1053 HReg argR = iselWordExpr_R(env, e->Iex.Binop.arg2);
1054 MIPSRH *argRH = iselWordExpr_RH(env, False /*signed */ ,
1061 addInstr(env, MIPSInstr_Alu(Malu_SLT, tmp, argL, argRH));
1062 addInstr(env, mk_iMOVds_RR(r_dst, argL));
1063 addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, r_dst, argR, tmp));
1069 HReg r_dst = newVRegI(env);
1070 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
1071 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
1072 addInstr(env, MIPSInstr_Mul(False/*Unsigned or Signed */ ,
1080 HReg r_dst = newVRegI(env);
1081 HReg tHi = newVRegI(env);
1082 HReg tLo = newVRegI(env);
1083 HReg tLo_1 = newVRegI(env);
1084 HReg tHi_1 = newVRegI(env);
1085 HReg mask = newVRegI(env);
1090 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
1091 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
1092 addInstr(env, MIPSInstr_Mul(syned /*Unsigned or Signed */ ,
1097 addInstr(env, MIPSInstr_Mfhi(tHi));
1098 addInstr(env, MIPSInstr_Mflo(tLo));
1100 addInstr(env, MIPSInstr_Shft(Mshft_SLL, False, tHi_1,
1103 addInstr(env, MIPSInstr_LI(mask, 0xffffffff));
1104 addInstr(env, MIPSInstr_Alu(Malu_AND, tLo_1, tLo,
1107 addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, tHi_1,
1116 r_srcL = iselFltExpr(env, e->Iex.Binop.arg1);
1117 r_srcR = iselFltExpr(env, e->Iex.Binop.arg2);
1119 r_srcL = iselDblExpr(env, e->Iex.Binop.arg1);
1120 r_srcR = iselDblExpr(env, e->Iex.Binop.arg2);
1122 HReg tmp = newVRegI(env);
1123 HReg r_ccMIPS = newVRegI(env);
1124 HReg r_ccIR = newVRegI(env);
1125 HReg r_ccIR_b0 = newVRegI(env);
1126 HReg r_ccIR_b2 = newVRegI(env);
1127 HReg r_ccIR_b6 = newVRegI(env);
1131 addInstr(env, MIPSInstr_FpCompare(Mfp_CMP_EQ, tmp, r_srcL, r_srcR));
1132 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, r_ccMIPS, tmp,
1135 addInstr(env, MIPSInstr_FpCompare(Mfp_CMP_UN, tmp, r_srcL, r_srcR));
1136 addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccMIPS, r_ccMIPS,
1139 addInstr(env, MIPSInstr_FpCompare(Mfp_CMP_LT, tmp, r_srcL, r_srcR));
1140 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tmp,
1142 addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccMIPS, r_ccMIPS,
1145 addInstr(env, MIPSInstr_FpCompare(Mfp_CMP_NGT,
1147 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tmp, tmp,
1150 addInstr(env, MIPSInstr_Alu(Malu_NOR, tmp, tmp, MIPSRH_Reg(tmp)));
1151 addInstr(env, MIPSInstr_Alu(Malu_AND, tmp, tmp,
1153 addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccMIPS, r_ccMIPS,
1166 addInstr(env, MIPSInstr_Shft(Mshft_SRL, True, r_ccIR_b0, r_ccMIPS,
1168 addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccIR_b0, r_ccMIPS,
1170 addInstr(env, MIPSInstr_Alu(Malu_AND, r_ccIR_b0, r_ccIR_b0,
1174 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, r_ccIR_b2, r_ccMIPS,
1176 addInstr(env, MIPSInstr_Alu(Malu_AND, r_ccIR_b2, r_ccIR_b2,
1180 addInstr(env, MIPSInstr_Shft(Mshft_SRL, True, r_ccIR_b6,
1182 addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccIR_b6, r_ccMIPS,
1184 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, r_ccIR_b6, r_ccIR_b6,
1186 addInstr(env, MIPSInstr_Alu(Malu_AND, r_ccIR_b6, r_ccIR_b6,
1190 addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccIR, r_ccIR_b0,
1192 addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccIR, r_ccIR,
1199 HReg tLo = newVRegI(env);
1200 HReg tHi = newVRegI(env);
1201 HReg mask = newVRegI(env);
1202 HReg tLo_1 = newVRegI(env);
1203 HReg tHi_1 = newVRegI(env);
1204 HReg r_dst = newVRegI(env);
1207 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
1208 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
1210 addInstr(env, MIPSInstr_Div(syned, True, r_srcL, r_srcR));
1211 addInstr(env, MIPSInstr_Mfhi(tHi));
1212 addInstr(env, MIPSInstr_Mflo(tLo));
1214 addInstr(env, MIPSInstr_Shft(Mshft_SLL, False, tHi_1, tHi,
1217 addInstr(env, MIPSInstr_LI(mask, 0xffffffff));
1218 addInstr(env, MIPSInstr_Alu(Malu_AND, tLo_1, tLo,
1221 addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, tHi_1,
1229 HReg tHi = iselWordExpr_R(env, e->Iex.Binop.arg1);
1230 HReg tLo = iselWordExpr_R(env, e->Iex.Binop.arg2);
1231 HReg tLo_1 = newVRegI(env);
1232 HReg tHi_1 = newVRegI(env);
1233 HReg r_dst = newVRegI(env);
1252 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tHi_1, tHi,
1254 addInstr(env, MIPSInstr_Alu(Malu_AND, tLo_1, tLo,
1256 addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, tHi_1,
1263 HReg tHi = iselWordExpr_R(env, e->Iex.Binop.arg1);
1264 HReg tLo = iselWordExpr_R(env, e->Iex.Binop.arg2);
1265 HReg tLo_1 = newVRegI(env);
1266 HReg tHi_1 = newVRegI(env);
1267 HReg r_dst = newVRegI(env);
1268 HReg mask = newVRegI(env);
1270 addInstr(env, MIPSInstr_Shft(Mshft_SLL, False, tHi_1, tHi,
1273 addInstr(env, MIPSInstr_LI(mask, 0xffffffff));
1274 addInstr(env, MIPSInstr_Alu(Malu_AND, tLo_1, tLo,
1276 addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, tHi_1,
1284 HReg valS = newVRegI(env);
1285 HReg tmpF = newVRegF(env);
1286 HReg valF = iselFltExpr(env, e->Iex.Binop.arg2);
1289 set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
1290 addInstr(env, MIPSInstr_FpConvert(Mfp_CVTLS, tmpF, valF));
1291 set_MIPS_rounding_default(env);
1295 addInstr(env, MIPSInstr_FpGpMove(MFpGpMove_dmfc1, valS, tmpF));
1303 valD = iselFltExpr(env, e->Iex.Binop.arg2);
1305 valD = iselDblExpr(env, e->Iex.Binop.arg2);
1306 HReg valS = newVRegF(env);
1307 HReg r_dst = newVRegI(env);
1310 set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
1311 addInstr(env, MIPSInstr_FpConvert(Mfp_CVTWD, valS, valD));
1312 set_MIPS_rounding_default(env);
1316 addInstr(env, MIPSInstr_FpGpMove(MFpGpMove_mfc1, r_dst, valS));
1351 HReg regL = iselWordExpr_R(env
1352 HReg regR = iselWordExpr_R(env, e->Iex.Binop.arg2);
1353 HReg res = newVRegI(env);
1354 addInstr(env, mk_iMOVds_RR(hregMIPS_GPR4(env->mode64), regL));
1355 addInstr(env, mk_iMOVds_RR(hregMIPS_GPR5(env->mode64), regR));
1358 addInstr(env, MIPSInstr_CallAlways( MIPScc_AL,
1361 addInstr(env, mk_iMOVds_RR(res, hregMIPS_GPR2(env->mode64)));
1381 HReg r_dst = newVRegI(env);
1382 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
1426 addInstr(env, MIPSInstr_Shft(Mshft_SLL, sz32, r_dst, r_src,
1428 addInstr(env, MIPSInstr_Shft(Mshft_SRA, sz32, r_dst, r_dst,
1435 HReg r_dst = newVRegI(env);
1436 HReg r_srcL = iselWordExpr_R(env, e->Iex.Unop.arg);
1439 addInstr(env, MIPSInstr_LI(r_dst, 0x1));
1440 addInstr(env, MIPSInstr_Alu(Malu_SUB, r_dst, r_dst, r_srcR));
1448 HReg r_dst = newVRegI(env);
1449 HReg r_srcL = iselWordExpr_R(env, e->Iex.Unop.arg);
1452 addInstr(env, MIPSInstr_Alu(Malu_NOR, r_dst, r_srcL, r_srcR));
1457 HReg fr_src = iselFltExpr(env, e->Iex.Unop.arg);
1458 HReg r_dst = newVRegI(env);
1462 addInstr(env, MIPSInstr_FpGpMove(MFpGpMove_mfc1, r_dst, fr_src));
1469 HReg fr_src = iselFltExpr(env, e->Iex.Unop.arg);
1470 HReg r_dst = newVRegI(env);
1474 addInstr(env, MIPSInstr_FpGpMove(MFpGpMove_dmfc1, r_dst, fr_src));
1482 valD = iselFltExpr(env, e->Iex.Binop.arg2);
1484 valD = iselDblExpr(env, e->Iex.Binop.arg2);
1485 HReg valS = newVRegF(env);
1486 HReg r_dst = newVRegI(env);
1488 set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
1489 addInstr(env, MIPSInstr_FpConvert(Mfp_CVTWD, valS, valD));
1490 set_MIPS_rounding_default(env);
1494 addInstr(env, MIPSInstr_FpGpMove(MFpGpMove_mfc1, r_dst, valS));
1503 return iselWordExpr_R(env, e->Iex.Unop.arg);
1506 HReg r_dst = newVRegI(env);
1507 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
1508 addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */,
1518 r_dst = newVRegI(env);
1519 r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
1520 addInstr(env, MIPSInstr_Alu(Malu_AND, r_dst, r_src,
1526 HReg r_dst = newVRegI(env);
1527 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
1528 addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */,
1541 HReg r_dst = newVRegI(env);
1542 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
1566 addInstr(env, MIPSInstr_Alu(Malu_AND, r_dst, r_src,
1572 HReg r_dst = newVRegI(env);
1573 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
1575 addInstr(env, MIPSInstr_Shft(Mshft_SLL, False /*!32bit shift */,
1577 addInstr(env, MIPSInstr_Shft(Mshft_SRL, False /*!32bit shift */,
1583 if (env->mode64) {
1584 HReg r_dst = newVRegI(env);
1585 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
1586 addInstr(env, MIPSInstr_Shft(Mshft_SRA, False /*64bit shift */,
1591 iselInt64Expr(&rHi, &rLo, env, e->Iex.Unop.arg);
1597 if (env->mode64) {
1598 HReg r_dst = newVRegI(env);
1599 r_dst = iselWordExpr_R(env, e->Iex.Unop.arg);
1603 iselInt64Expr(&rHi, &rLo, env, e->Iex.Unop.arg);
1609 vassert(env->mode64);
1610 HReg r_dst = newVRegI(env);
1611 r_dst = iselWordExpr_R(env, e->Iex.Unop.arg);
1616 HReg r_dst = newVRegI(env);
1617 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
1619 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /*!32bit shift */,
1626 HReg r_dst = newVRegI(env);
1627 HReg tmp = newVRegI(env);
1628 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
1631 addInstr(env, MIPSInstr_Alu(Malu_AND, tmp, r_src,
1633 addInstr(env, MIPSInstr_Cmp(False, True, r_dst, tmp,
1639 HReg r_dst = newVRegI(env);
1640 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
1642 addInstr(env, MIPSInstr_Cmp(False, True, r_dst, r_src,
1648 HReg r_dst = newVRegI(env);
1649 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
1651 addInstr(env, MIPSInstr_Alu(Malu_SUB, r_dst, hregMIPS_GPR0(mode64),
1654 addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, r_dst,
1656 addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, r_dst, r_dst,
1667 HReg r_dst = newVRegI(env);
1668 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
1670 addInstr(env, MIPSInstr_Alu(op, r_dst,
1673 addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, r_dst,
1681 HReg r_dst = newVRegI(env);
1682 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
1684 addInstr(env, MIPSInstr_Unary(op, r_dst, r_src));
1690 HReg r_dst = newVRegI(env);
1692 if (env->mode64) {
1693 r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
1695 r_src = newVRegI(env);
1696 iselInt64Expr(&hi, &lo, env, e->Iex.Unop.arg);
1697 addInstr(env, MIPSInstr_Alu(Malu_OR, r_src, lo, MIPSRH_Reg(hi)));
1699 addInstr(env, MIPSInstr_Cmp(False, !(env->mode64), r_dst, r_src,
1706 HReg tmp2 = newVRegI(env);
1707 vassert(env->mode64);
1708 tmp1 = iselWordExpr_R(env, e->Iex.Unop.arg);
1710 addInstr(env, MIPSInstr_Alu(Malu_DSUB, tmp2, hregMIPS_GPR0(mode64),
1713 addInstr(env, MIPSInstr_Alu(Malu_OR, tmp2, tmp2, MIPSRH_Reg(tmp1)));
1714 addInstr(env, MIPSInstr_Shft(Mshft_SRA, False, tmp2, tmp2,
1722 iselInt128Expr(&rHi, &rLo, env, e->Iex.Unop.arg);
1729 iselInt128Expr(&rHi, &rLo, env, e->Iex.Unop.arg);
1762 HReg regL = iselWordExpr_R(env, e->Iex.Unop.arg);
1763 HReg res = newVRegI(env);
1764 addInstr(env, mk_iMOVds_RR(hregMIPS_GPR4(env->mode64), regL));
1766 addInstr(env, MIPSInstr_CallAlways( MIPScc_AL,
1769 addInstr(env, mk_iMOVds_RR(res, hregMIPS_GPR2(env->mode64)));
1780 HReg r_dst = newVRegI(env);
1784 addInstr(env, MIPSInstr_Load(toUChar(sizeofIRType(ty)), r_dst, am_addr,
1795 typeOfIRExpr(env->type_env, e->Iex.ITE.cond) == Ity_I1) {
1796 HReg r_dst = iselWordExpr_R(env, e->Iex.ITE.iffalse);
1797 HReg r1 = iselWordExpr_R(env, e->Iex.ITE.iftrue);
1798 HReg r_cond = iselWordExpr_R(env, e->Iex.ITE.cond);
1803 addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, r_dst, r1, r_cond));
1813 HReg r_dst = newVRegI(env);
1833 addInstr(env, MIPSInstr_LI(r_dst, (ULong) l));
1839 HReg r_dst = newVRegI(env);
1851 doHelperCall(&addToSp, &rloc, env, NULL/*guard*/, e->Iex.CCall.cee,
1857 addInstr(env, mk_iMOVds_RR(r_dst, hregMIPS_GPR2(mode64)));
1884 static MIPSRH *iselWordExpr_RH(ISelEnv * env, Bool syned, IRExpr * e)
1886 MIPSRH *ri = iselWordExpr_RH_wrk(env, syned, e);
1895 vassert(hregClass(ri->Mrh.Reg.reg) == HRcGPR(env->mode64));
1904 static MIPSRH *iselWordExpr_RH_wrk(ISelEnv * env, Bool syned, IRExpr * e)
1908 IRType ty = typeOfIRExpr(env->type_env, e);
1910 ((ty == Ity_I64) && env->mode64));
1919 vassert(env->mode64);
1945 return MIPSRH_Reg(iselWordExpr_R(env, e));
1954 static MIPSRH *iselWordExpr_RH5u(ISelEnv * env, IRExpr * e)
1957 ri = iselWordExpr_RH5u_wrk(env, e);
1974 static MIPSRH *iselWordExpr_RH5u_wrk(ISelEnv * env, IRExpr * e)
1976 IRType ty = typeOfIRExpr(env->type_env, e);
1987 return MIPSRH_Reg(iselWordExpr_R(env, e));
1993 static MIPSRH *iselWordExpr_RH6u ( ISelEnv * env, IRExpr * e )
1996 ri = iselWordExpr_RH6u_wrk(env, e);
2004 vassert(hregClass(ri->Mrh.Reg.reg) == HRcGPR(env->mode64));
2013 static MIPSRH *iselWordExpr_RH6u_wrk ( ISelEnv * env, IRExpr * e )
2015 IRType ty = typeOfIRExpr(env->type_env, e);
2028 return MIPSRH_Reg(iselWordExpr_R(env, e));
2037 static MIPSCondCode iselCondCode(ISelEnv * env, IRExpr * e)
2039 MIPSCondCode cc = iselCondCode_wrk(env,e);
2045 static MIPSCondCode iselCondCode_wrk(ISelEnv * env, IRExpr * e)
2048 vassert(typeOfIRExpr(env->type_env, e) == Ity_I1);
2068 HReg dst = newVRegI(env);
2069 HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1);
2070 HReg r2 = iselWordExpr_R(env, e->Iex.Binop.arg2);
2122 addInstr(env, MIPSInstr_Cmp(syned, size32, dst, r1, r2, cc));
2126 addInstr(env, MIPSInstr_Store(4,
2133 HReg r_dst = newVRegI(env);
2134 HReg r_srcL = iselWordExpr_R(env, e->Iex.Unop.arg);
2137 addInstr(env, MIPSInstr_LI(r_dst, 0x1));
2138 addInstr(env, MIPSInstr_Alu(Malu_SUB, r_dst, r_dst, r_srcR));
2142 addInstr(env, MIPSInstr_Store(4,
2149 HReg r_dst = iselWordExpr_R_wrk(env, e);
2153 addInstr(env, MIPSInstr_Store(4,
2175 static void iselInt128Expr(HReg * rHi, HReg * rLo, ISelEnv * env, IRExpr * e)
2177 vassert(env->mode64);
2178 iselInt128Expr_wrk(rHi, rLo, env, e);
2179 vassert(hregClass(*rHi) == HRcGPR(env->mode64));
2181 vassert(hregClass(*rLo) == HRcGPR(env->mode64));
2186 static void iselInt128Expr_wrk(HReg * rHi, HReg * rLo, ISelEnv * env,
2190 vassert(typeOfIRExpr(env->type_env, e) == Ity_I128);
2194 lookupIRTempPair(rHi, rLo, env, e->Iex.RdTmp.tmp);
2204 HReg tLo = newVRegI(env);
2205 HReg tHi = newVRegI(env);
2207 HReg r_dst = newVRegI(env);
2208 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
2209 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
2210 addInstr(env, MIPSInstr_Mul(syned, True, False /*64bit mul */ ,
2212 addInstr(env, MIPSInstr_Mfhi(tHi));
2213 addInstr(env, MIPSInstr_Mflo(tLo));
2221 *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1);
2222 *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2);
2226 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
2227 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
2228 HReg tLo = newVRegI(env);
2229 HReg tHi = newVRegI(env);
2232 addInstr(env, MIPSInstr_Div(syned, False, r_srcL, r_srcR));
2233 addInstr(env, MIPSInstr_Mfhi(tHi));
2234 addInstr(env, MIPSInstr_Mflo(tLo));
2244 iselInt128Expr(&rHi1, &rLo1, env, e->Iex.Binop.arg1);
2246 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
2247 HReg tLo = newVRegI(env);
2248 HReg tHi = newVRegI(env);
2251 addInstr(env, MIPSInstr_Div(syned, False, rLo1, r_srcR));
2252 addInstr(env, MIPSInstr_Mfhi(tHi));
2253 addInstr(env, MIPSInstr_Mflo(tLo));
2276 static void iselInt64Expr(HReg * rHi, HReg * rLo, ISelEnv * env, IRExpr * e)
2278 vassert(!env->mode64);
2279 iselInt64Expr_wrk(rHi, rLo, env, e);
2287 static void iselInt64Expr_wrk(HReg * rHi, HReg * rLo, ISelEnv * env, IRExpr * e)
2290 vassert(typeOfIRExpr(env->type_env, e) == Ity_I64);
2294 lookupIRTemp64(rHi, rLo, env, e->Iex.RdTmp.tmp);
2299 HReg tLo = newVRegI(env);
2300 HReg tHi = newVRegI(env);
2301 HReg r_addr = iselWordExpr_R(env, e->Iex.Load.addr);
2302 addInstr(env, MIPSInstr_Load(4, tHi, MIPSAMode_IR(0, r_addr), mode64));
2303 addInstr(env, MIPSInstr_Load(4, tLo, MIPSAMode_IR(4, r_addr), mode64));
2314 HReg tLo = newVRegI(env);
2315 HReg tHi = newVRegI(env);
2320 addInstr(env, MIPSInstr_LI(tLo, (ULong) wLo));
2324 addInstr(env, MIPSInstr_LI(tHi, (ULong) wHi));
2325 addInstr(env, MIPSInstr_LI(tLo, (ULong) wLo));
2335 HReg tLo = newVRegI(env);
2336 HReg tHi = newVRegI(env);
2340 addInstr(env, MIPSInstr_Load(4, tLo, am_addr, mode64));
2341 addInstr(env, MIPSInstr_Load(4, tHi, nextMIPSAModeInt(am_addr), mode64));
2349 vassert(typeOfIRExpr(env->type_env, e->Iex.ITE.cond) == Ity_I1);
2352 HReg desLo = newVRegI(env);
2353 HReg desHi = newVRegI(env);
2354 HReg cond = iselWordExpr_R(env, e->Iex.ITE.cond);
2358 iselInt64Expr(&expr0Hi, &expr0Lo, env, e->Iex.ITE.iffalse);
2359 iselInt64Expr(&expr1Hi, &expr1Lo, env, e->Iex.ITE.iftrue);
2365 addInstr(env, mk_iMOVds_RR(desLo, expr0Lo));
2366 addInstr(env, mk_iMOVds_RR(desHi, expr0Hi));
2367 addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, desLo, expr1Lo, cond));
2368 addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, desHi, expr1Hi, cond));
2384 HReg tHi = newVRegI(env);
2385 HReg tHi1 = newVRegI(env);
2386 HReg tLo = newVRegI(env);
2388 carryBit = newVRegI(env);
2393 iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
2394 iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
2395 addInstr(env, MIPSInstr_Alu(Malu_ADD, tLo, xLo, MIPSRH_Reg(yLo)));
2398 addInstr(env, MIPSInstr_Cmp(False, size32, carryBit, tLo, xLo, cc));
2400 addInstr(env, MIPSInstr_Alu(Malu_ADD, tHi1, xHi, MIPSRH_Reg(yHi)));
2401 addInstr(env, MIPSInstr_Alu(Malu_ADD, tHi, tHi1,
2413 HReg tHi = newVRegI(env);
2414 HReg tLo = newVRegI(env);
2416 borrow = newVRegI(env);
2418 iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
2419 iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
2421 addInstr(env, MIPSInstr_Alu(Malu_SUB, tLo, xLo, MIPSRH_Reg(yLo)));
2424 addInstr(env, MIPSInstr_Cmp(False, size32, borrow, xLo, yLo, cc));
2426 addInstr(env, MIPSInstr_Alu(Malu_ADD, yHi, yHi,
2428 addInstr(env, MIPSInstr_Alu(Malu_SUB, tHi, xHi, MIPSRH_Reg(yHi)));
2436 HReg tLo = newVRegI(env);
2437 HReg tHi = newVRegI(env);
2438 HReg r_dst = newVRegI(env);
2440 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1);
2441 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
2443 addInstr(env, MIPSInstr_Mul(syned /*Unsigned or Signed */,
2446 addInstr(env, MIPSInstr_Mfhi(tHi));
2447 addInstr(env, MIPSInstr_Mflo(tLo));
2456 HReg tLo = newVRegI(env);
2457 HReg tHi = newVRegI(env);
2459 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2);
2461 iselInt64Expr(&r_sHi, &r_sLo, env, e->Iex.Binop.arg1);
2462 addInstr(env, MIPSInstr_Div(syned, True, r_sLo, r_srcR));
2463 addInstr(env, MIPSInstr_Mfhi(tHi));
2464 addInstr(env, MIPSInstr_Mflo(tLo));
2473 *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1);
2474 *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2);
2482 HReg tLo = newVRegI(env);
2483 HReg tHi = newVRegI(env);
2486 iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
2487 iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
2488 addInstr(env, MIPSInstr_Alu(op, tHi, xHi, MIPSRH_Reg(yHi)));
2489 addInstr(env, MIPSInstr_Alu(op, tLo, xLo, MIPSRH_Reg(yLo)));
2511 HReg a0tmp = newVRegI(env);
2512 HReg a2 = newVRegI(env);
2513 HReg a3 = newVRegI(env);
2514 HReg v0 = newVRegI(env);
2515 HReg v1 = newVRegI(env);
2516 HReg zero = newVRegI(env);
2519 iselInt64Expr(&a1, &a0, env, e->Iex.Binop.arg1);
2520 sa = iselWordExpr_RH6u(env, e->Iex.Binop.arg2);
2523 addInstr(env, MIPSInstr_LI(a2, sa->Mrh.Imm.imm16));
2526 addInstr(env, MIPSInstr_Alu(Malu_AND, a2, sa->Mrh.Reg.reg,
2530 addInstr(env, MIPSInstr_LI(zero, 0x00000000));
2532 addInstr(env, MIPSInstr_Alu(Malu_NOR, v0, zero, MIPSRH_Reg(a2)));
2534 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */,
2537 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */,
2540 addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */,
2543 addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */,
2546 addInstr(env, MIPSInstr_Alu(Malu_AND, a0tmp, a2,
2549 addInstr(env, MIPSInstr_Alu(Malu_OR, v0, a3, MIPSRH_Reg(v0)));
2552 addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, v0, v1, a0tmp));
2554 addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, v1, zero, a0tmp));
2575 HReg a2 = newVRegI(env);
2576 HReg a2tmp = newVRegI(env);
2577 HReg a3 = newVRegI(env);
2578 HReg v0 = newVRegI(env);
2579 HReg v1 = newVRegI(env);
2580 HReg zero = newVRegI(env);
2583 iselInt64Expr(&a0, &a1, env, e->Iex.Binop.arg1);
2584 sa = iselWordExpr_RH6u(env, e->Iex.Binop.arg2);
2587 addInstr(env, MIPSInstr_LI(a2, sa->Mrh.Imm.imm16));
2590 addInstr(env, MIPSInstr_Alu(Malu_AND, a2, sa->Mrh.Reg.reg,
2594 addInstr(env, MIPSInstr_LI(zero, 0x00000000));
2596 addInstr(env, MIPSInstr_Alu(Malu_NOR, v0, zero, MIPSRH_Reg(a2)));
2598 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */,
2601 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */,
2604 addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */,
2607 addInstr(env, MIPSInstr_Alu(Malu_AND, v0, a2,
2610 addInstr(env, MIPSInstr_Alu(Malu_OR, v1, a3, MIPSRH_Reg(v1)));
2612 addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */,
2616 addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, v1, a2tmp, v0));
2618 addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, a2tmp, zero, v0));
2620 addInstr(env, mk_iMOVds_RR(v0, a2tmp));
2644 HReg a2 = newVRegI(env);
2645 HReg a3 = newVRegI(env);
2646 HReg v0 = newVRegI(env);
2647 HReg v1 = newVRegI(env);
2648 HReg zero = newVRegI(env);
2651 iselInt64Expr(&a1, &a0, env, e->Iex.Binop.arg1);
2652 sa = iselWordExpr_RH6u(env, e->Iex.Binop.arg2);
2655 addInstr(env, MIPSInstr_LI(a2, sa->Mrh.Imm.imm16));
2658 addInstr(env, MIPSInstr_Alu(Malu_AND, a2, sa->Mrh.Reg.reg,
2662 addInstr(env, MIPSInstr_LI(zero, 0x00000000));
2664 addInstr(env, MIPSInstr_Alu(Malu_NOR, v0, zero, MIPSRH_Reg(a2)));
2666 addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */,
2669 addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */,
2672 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */,
2675 addInstr(env, MIPSInstr_Alu(Malu_AND, v0, a2,
2678 addInstr(env, MIPSInstr_Alu(Malu_OR, v1, a3, MIPSRH_Reg(v1)));
2680 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */,
2684 addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, v1, a2, v0));
2686 addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, a2, zero, v0));
2687 addInstr(env, mk_iMOVds_RR(v0, a2));
2710 HReg a0tmp = newVRegI(env);
2711 HReg a1tmp = newVRegI(env);
2712 HReg a2 = newVRegI(env);
2713 HReg a3 = newVRegI(env);
2714 HReg v0 = newVRegI(env);
2715 HReg v1 = newVRegI(env);
2716 HReg zero = newVRegI(env);
2719 iselInt64Expr(&a1, &a0, env, e->Iex.Binop.arg1);
2720 sa = iselWordExpr_RH6u(env, e->Iex.Binop.arg2);
2723 addInstr(env, MIPSInstr_LI(a2, sa->Mrh.Imm.imm16));
2726 addInstr(env, MIPSInstr_Alu(Malu_AND, a2, sa->Mrh.Reg.reg,
2730 addInstr(env, MIPSInstr_LI(zero, 0x00000000));
2732 addInstr(env, MIPSInstr_Alu(Malu_NOR, v0, zero, MIPSRH_Reg(a2)));
2734 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */,
2737 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True /* 32bit shift */,
2740 addInstr(env, MIPSInstr_Shft(Mshft_SRL, True /* 32bit shift */,
2743 addInstr(env, MIPSInstr_Shft(Mshft_SRA, True /* 32bit shift */,
2746 addInstr(env, MIPSInstr_Alu(Malu_AND, a0tmp, a2,
2749 addInstr(env, MIPSInstr_Shft(Mshft_SRA, True /* 32bit shift */,
2752 addInstr(env, MIPSInstr_Alu(Malu_OR, v0, a3, MIPSRH_Reg(v0)));
2755 addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, v0, v1, a0tmp));
2757 addInstr(env, MIPSInstr_MoveCond(MMoveCond_movn, v1, a1tmp, a0tmp));
2765 HReg tmpD = newVRegD(env);
2766 HReg valF = iselFltExpr(env, e->Iex.Binop.arg2);
2767 HReg tLo = newVRegI(env);
2768 HReg tHi = newVRegI(env);
2772 set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
2773 env, MIPSInstr_FpConvert(Mfp_CVTLS, tmpD, valF));
2774 set_MIPS_rounding_default(env);
2776 sub_from_sp(env, 16); /* Move SP down 16 bytes */
2780 addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 8, tmpD,
2784 addInstr(env, MIPSInstr_Load(4, tLo, am_addr, mode64));
2785 addInstr(env, MIPSInstr_Load(4, tHi, nextMIPSAModeFloat(am_addr),
2788 addInstr(env, MIPSInstr_Load(4, tHi, am_addr, mode64));
2789 addInstr(env, MIPSInstr_Load(4, tLo, nextMIPSAModeFloat(am_addr),
2794 add_to_sp(env, 16);
2811 HReg tLo = newVRegI(env);
2812 HReg tHi = newVRegI(env);
2813 HReg src = iselWordExpr_R(env, e->Iex.Unop.arg);
2814 HReg tmp = newVRegI(env);
2816 addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tmp, src,
2818 addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, tmp, tmp,
2821 addInstr(env, mk_iMOVds_RR(tHi, tmp));
2822 addInstr(env, mk_iMOVds_RR(tLo, tmp));
2831 HReg tLo = newVRegI(env);
2832 HReg tHi = newVRegI(env);
2833 HReg src = iselWordExpr_R(env, e->Iex.Unop.arg);
2834 addInstr(env, mk_iMOVds_RR(tHi, src));
2835 addInstr(env, mk_iMOVds_RR(tLo, src));
2836 addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, tHi, tHi,
2845 HReg tLo = newVRegI(env);
2846 HReg tHi = newVRegI(env);
2847 HReg src = iselWordExpr_R(env, e->Iex.Unop.arg);
2848 addInstr(env, MIPSInstr_Alu(Malu_AND, tLo, src,
2850 addInstr(env, MIPSInstr_Alu(Malu_ADD, tHi, hregMIPS_GPR0(mode64),
2859 HReg tLo = newVRegI(env);
2860 HReg tHi = newVRegI(env);
2861 HReg src = iselWordExpr_R(env, e->Iex.Unop.arg);
2862 addInstr(env, mk_iMOVds_RR(tLo, src));
2863 addInstr(env, MIPSInstr_Alu(Malu_ADD, tHi, hregMIPS_GPR0(mode64),
2872 HReg tHi = newVRegI(env);
2873 HReg tLo = newVRegI(env);
2874 HReg tmp = newVRegI(env);
2875 HReg tmp1 = newVRegI(env);
2876 HReg tmp2 = newVRegI(env);
2877 HReg zero = newVRegI(env);
2881 iselInt64Expr(&yHi, &yLo, env, e->Iex.Unop.arg);
2883 addInstr(env, MIPSInstr_LI(zero, 0x00000000));
2886 addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp2, zero, MIPSRH_Reg(yLo)));
2887 addInstr(env, MIPSInstr_Cmp(False, True, tmp1, zero, tmp2, cc));
2888 addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp, zero, MIPSRH_Reg(yHi)));
2889 addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp1, tmp, MIPSRH_Reg(tmp1)));
2894 addInstr(env, MIPSInstr_Alu(Malu_OR, tHi, yHi, MIPSRH_Reg(tmp1)));
2895 addInstr(env, MIPSInstr_Alu(Malu_OR, tLo, yLo, MIPSRH_Reg(tmp2)));
2903 HReg tmp1 = newVRegI(env);
2904 HReg tmp2 = newVRegI(env);
2906 iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg);
2908 addInstr(env, MIPSInstr_Alu(Malu_OR, tmp1, srcLo,
2912 addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp2, hregMIPS_GPR0(mode64),
2915 addInstr(env, MIPSInstr_Alu(Malu_OR, tmp2, tmp2, MIPSRH_Reg(tmp1)));
2916 addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, tmp2, tmp2,
2924 HReg tLo = newVRegI(env);
2925 HReg tHi = newVRegI(env);
2927 HReg fr_src = iselDblExpr(env, e->Iex.Unop.arg);
2929 sub_from_sp(env, 16); /* Move SP down 16 bytes */
2933 addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 8, fr_src,
2937 addInstr(env, MIPSInstr_Load(4, tLo, am_addr, mode64));
2938 addInstr(env, MIPSInstr_Load(4, tHi, nextMIPSAModeFloat(am_addr),
2941 addInstr(env, MIPSInstr_Load(4, tHi, am_addr, mode64));
2942 addInstr(env, MIPSInstr_Load(4, tLo, nextMIPSAModeFloat(am_addr),
2947 add_to_sp(env, 16);
2973 static HReg iselFltExpr(ISelEnv * env, IRExpr * e)
2975 HReg r = iselFltExpr_wrk(env, e);
2981 static HReg iselFltExpr_wrk(ISelEnv * env, IRExpr * e)
2983 IRType ty = typeOfIRExpr(env->type_env, e);
2987 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
2994 MIPSAMode *am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, ty);
2996 r_dst = newVRegD(env);
2997 addInstr(env, MIPSInstr_FpLdSt(True /*load */, 8, r_dst, am_addr));
2999 r_dst = newVRegF(env);
3000 addInstr(env, MIPSInstr_FpLdSt(True /*load */, 4, r_dst, am_addr));
3010 r_dst = newVRegD(env);
3011 addInstr(env, MIPSInstr_FpLdSt(True /*load */, 8, r_dst, am_addr));
3013 r_dst = newVRegF(env);
3014 addInstr(env, MIPSInstr_FpLdSt(True /*load */, 4, r_dst, am_addr));
3022 HReg fr_src = iselWordExpr_R(env, e->Iex.Unop.arg);
3023 HReg r_dst = newVRegF(env);
3027 addInstr(env, MIPSInstr_FpGpMove(MFpGpMove_mtc1, r_dst, fr_src));
3033 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
3034 HReg dst = newVRegD(env);
3036 addInstr(env, MIPSInstr_FpConvert(Mfp_CVTDS, dst, src));
3042 HReg fr_src = iselWordExpr_R(env, e->Iex.Unop.arg);
3043 r_dst = newVRegF(env);
3046 addInstr(env, MIPSInstr_FpGpMove(MFpGpMove_dmtc1, r_dst, fr_src));
3049 r_dst = newVRegD(env);
3050 iselInt64Expr(&Hi, &Lo, env, e->Iex.Unop.arg);
3051 r_dst = mk_LoadRR32toFPR(env, Hi, Lo); /* 2*I32 -> F64 */
3057 HReg dst = newVRegF(env);
3058 HReg tmp = newVRegF(env);
3059 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
3063 addInstr(env, MIPSInstr_FpGpMove(MFpGpMove_mtc1, tmp, r_src));
3066 addInstr(env, MIPSInstr_FpConvert(Mfp_CVTDW, dst, tmp));
3073 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
3074 HReg dst = newVRegF(env);
3075 addInstr(env, MIPSInstr_FpUnary(sz32 ? Mfp_ABSS : Mfp_ABSD, dst, src));
3081 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
3082 HReg dst = newVRegF(env);
3083 addInstr(env, MIPSInstr_FpUnary(sz32 ? Mfp_NEGS : Mfp_NEGD, dst, src));
3088 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
3089 HReg dst = newVRegF(env);
3090 addInstr(env, MIPSInstr_FpConvert(Mfp_TRULD, dst, src));
3095 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
3096 HReg dst = newVRegF(env);
3097 addInstr(env, MIPSInstr_FpConvert(Mfp_ROUNDLD, dst, src));
3102 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
3103 HReg dst = newVRegF(env);
3104 addInstr(env, MIPSInstr_FpConvert(Mfp_FLOORLD, dst, src));
3109 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
3110 HReg dst = newVRegF(env);
3111 addInstr(env, MIPSInstr_FpConvert(Mfp_CEILLD, dst, src));
3131 HReg argL = iselFltExpr(env, e->Iex.Triop.details->arg2);
3132 HReg argR = iselFltExpr(env, e->Iex.Triop.details->arg3);
3133 HReg dst = newVRegF(env);
3166 set_MIPS_rounding_mode(env, e->Iex.Triop.details->arg1);
3167 addInstr(env, MIPSInstr_FpBinary(op, dst, argL, argR));
3168 set_MIPS_rounding_default(env);
3181 valD = iselFltExpr(env, e->Iex.Binop.arg2);
3183 valD = iselDblExpr(env, e->Iex.Binop.arg2);
3184 HReg valS = newVRegF(env);
3186 set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
3187 addInstr(env, MIPSInstr_FpConvert(Mfp_CVTSD, valS, valD));
3188 set_MIPS_rounding_default(env);
3193 HReg valS = newVRegF(env);
3194 HReg valF = iselFltExpr(env, e->Iex.Binop.arg2);
3196 set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
3197 addInstr(env, MIPSInstr_FpConvert(Mfp_CVTWS, valS, valF));
3198 set_MIPS_rounding_default(env);
3203 HReg valS = newVRegF(env);
3204 HReg valF = iselFltExpr(env, e->Iex.Binop.arg2);
3206 set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
3207 addInstr(env, MIPSInstr_FpConvert(Mfp_CVTLD, valS, valF));
3208 set_MIPS_rounding_default(env);
3213 HReg r_dst = newVRegF(env);
3214 HReg fr_src = iselWordExpr_R(env, e->Iex.Binop.arg2);
3215 HReg tmp = newVRegF(env);
3219 addInstr(env, MIPSInstr_FpGpMove(MFpGpMove_mtc1, tmp, fr_src));
3221 set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
3222 addInstr(env, MIPSInstr_FpConvert(Mfp_CVTSW, r_dst, tmp));
3223 set_MIPS_rounding_default(env);
3229 HReg r_dst = newVRegF(env);
3233 tmp = newVRegF(env);
3234 fr_src = iselWordExpr_R(env, e->Iex.Binop.arg2);
3236 sub_from_sp(env, 8);
3240 addInstr(env, MIPSInstr_Store(8, am_addr, fr_src, mode64));
3243 addInstr(env, MIPSInstr_FpLdSt(True /*load */, 8, tmp, am_addr));
3246 add_to_sp(env, 8);
3249 tmp = newVRegD(env);
3250 iselInt64Expr(&Hi, &Lo, env, e->Iex.Binop.arg2);
3251 tmp = mk_LoadRR32toFPR(env, Hi, Lo); /* 2*I32 -> F64 */
3254 set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
3255 env, MIPSInstr_FpConvert(Mfp_CVTDL, r_dst, tmp));
3256 set_MIPS_rounding_default(env);
3262 HReg r_dst = newVRegF(env);
3266 tmp = newVRegF(env);
3267 fr_src = iselWordExpr_R(env, e->Iex.Binop.arg2);
3269 sub_from_sp(env, 8);
3273 addInstr(env, MIPSInstr_Store(8, am_addr, fr_src, mode64));
3276 addInstr(env, MIPSInstr_FpLdSt(True /*load */, 8, tmp, am_addr));
3279 add_to_sp(env, 8);
3282 tmp = newVRegD(env);
3283 iselInt64Expr(&Hi, &Lo, env, e->Iex.Binop.arg2);
3284 tmp = mk_LoadRR32toFPR(env, Hi, Lo); /* 2*I32 -> F64 */
3287 set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
3288 addInstr(env, MIPSInstr_FpConvert(Mfp_CVTSL, r_dst, tmp));
3289 set_MIPS_rounding_default(env);
3297 HReg src = iselFltExpr(env, e->Iex.Binop.arg2);
3298 HReg dst = newVRegF(env);
3299 set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
3300 addInstr(env, MIPSInstr_FpUnary(sz32 ? Mfp_SQRTS : Mfp_SQRTD, dst,
3302 set_MIPS_rounding_default(env);
3334 HReg dst = newVRegF(env);
3335 HReg src1 = iselFltExpr(env, e->Iex.Qop.details->arg2);
3336 HReg src2 = iselFltExpr(env, e->Iex.Qop.details->arg3);
3337 HReg src3 = iselFltExpr(env, e->Iex.Qop.details->arg4);
3338 set_MIPS_rounding_mode(env, e->Iex.Qop.details->arg1);
3339 addInstr(env, MIPSInstr_FpTernary(op, dst,
3341 set_MIPS_rounding_default(env);
3379 HReg fsrc = iselDblExpr(env, e->Iex.Unop.arg);
3380 HReg fdst = newVRegF(env);
3383 sub_from_sp(env, 16);
3385 addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 4, fsrc, zero_r1));
3387 addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 4, fdst, zero_r1));
3388 add_to_sp(env, 16);
3395 && typeOfIRExpr(env->type_env, e->Iex.ITE.cond) == Ity_I1) {
3397 HReg r0 = iselFltExpr(env, e->Iex.ITE.iffalse);
3398 HReg r1 = iselFltExpr(env, e->Iex.ITE.iftrue);
3399 HReg r_cond = iselWordExpr_R(env, e->Iex.ITE.cond);
3400 HReg r_dst = newVRegF(env);
3401 addInstr(env, MIPSInstr_FpUnary(Mfp_MOVD, r_dst, r0));
3402 addInstr(env, MIPSInstr_MoveCond(MFpMoveCond_movnd, r_dst, r1,
3413 static HReg iselDblExpr(ISelEnv * env, IRExpr * e)
3415 HReg r = iselDblExpr_wrk(env, e);
3422 static HReg iselDblExpr_wrk(ISelEnv * env, IRExpr * e)
3424 IRType ty = typeOfIRExpr(env->type_env, e);
3429 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
3434 HReg r_dst = newVRegD(env);
3437 am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, ty);
3438 addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 8, r_dst, am_addr));
3445 HReg r_dst = newVRegD(env);
3448 addInstr(env, MIPSInstr_FpLdSt(True /*load */ , 8, r_dst, am_addr));
3463 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
3464 HReg dst = newVRegD(env);
3466 addInstr(env, MIPSInstr_FpConvert(Mfp_CVTDS, dst, src));
3471 HReg dst = newVRegD(env);
3473 iselInt64Expr(&Hi, &Lo, env, e->Iex.Unop.arg);
3475 dst = mk_LoadRR32toFPR(env, Hi, Lo); /* 2*I32 -> F64 */
3480 HReg dst = newVRegD(env);
3481 HReg tmp = newVRegF(env);
3482 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg);
3486 addInstr(env, MIPSInstr_FpGpMove(MFpGpMove_mtc1, tmp, r_src));
3489 addInstr(env, MIPSInstr_FpConvert(Mfp_CVTDW, dst, tmp));
3498 HReg src = iselDblExpr(env, e->Iex.Unop.arg);
3499 HReg dst = newVRegD(env);
3500 addInstr(env, MIPSInstr_FpUnary(fpop, dst, src));
3508 HReg src = iselDblExpr(env, e->Iex.Binop.arg2);
3509 HReg dst = newVRegD(env);
3511 set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
3512 addInstr(env, MIPSInstr_FpConvert(Mfp_CVTLD, dst, src));
3513 set_MIPS_rounding_default(env);
3519 HReg src = iselDblExpr(env, e->Iex.Binop.arg2);
3520 HReg dst = newVRegD(env);
3521 set_MIPS_rounding_mode(env, e->Iex.Binop.arg1);
3522 addInstr(env, MIPSInstr_FpUnary(Mfp_SQRTD, dst, src));
3523 set_MIPS_rounding_default(env);
3541 HReg argL = iselDblExpr(env, e->Iex.Triop.details->arg2);
3542 HReg argR = iselDblExpr(env, e->Iex.Triop.details->arg3);
3543 HReg dst = newVRegD(env);
3563 set_MIPS_rounding_mode(env, e->Iex.Triop.details->arg1);
3564 addInstr(env, MIPSInstr_FpBinary(op, dst, argL, argR));
3565 set_MIPS_rounding_default(env);
3596 HReg dst = newVRegD(env);
3597 HReg src1 = iselDblExpr(env, e->Iex.Qop.details->arg2);
3598 HReg src2 = iselDblExpr(env, e->Iex.Qop.details->arg3);
3599 HReg src3 = iselDblExpr(env, e->Iex.Qop.details->arg4);
3600 set_MIPS_rounding_mode(env, e->Iex.Qop.details->arg1);
3601 addInstr(env, MIPSInstr_FpTernary(op, dst,
3603 set_MIPS_rounding_default(env);
3615 && typeOfIRExpr(env->type_env, e->Iex.ITE.cond) == Ity_I1) {
3616 HReg r0 = iselDblExpr(env, e->Iex.ITE.iffalse);
3617 HReg r1 = iselDblExpr(env, e->Iex.ITE.iftrue);
3618 HReg r_cond = iselWordExpr_R(env, e->Iex.ITE.cond);
3619 HReg r_dst = newVRegD(env);
3621 addInstr(env, MIPSInstr_FpUnary(Mfp_MOVD, r_dst, r0));
3622 addInstr(env, MIPSInstr_MoveCond(MFpMoveCond_movnd, r_dst, r1,
3637 static void iselStmt(ISelEnv * env, IRStmt * stmt)
3650 IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data);
3653 am_addr = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd);
3657 HReg r_src = iselWordExpr_R(env, stmt->Ist.Store.data);
3658 addInstr(env, MIPSInstr_Store(toUChar(sizeofIRType(tyd)),
3664 HReg r_addr = iselWordExpr_R(env, stmt->Ist.Store.addr);
3666 iselInt64Expr(&vHi, &vLo, env, stmt->Ist.Store.data);
3668 addInstr(env, MIPSInstr_Store(toUChar(sizeofIRType(Ity_I32)),
3670 addInstr(env, MIPSInstr_Store(toUChar(sizeofIRType(Ity_I32)),
3675 HReg fr_src = iselFltExpr(env, stmt->Ist.Store.data);
3676 addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 4, fr_src,
3681 HReg fr_src = iselFltExpr(env, stmt->Ist.Store.data);
3682 addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 8, fr_src,
3687 HReg fr_src = iselDblExpr(env, stmt->Ist.Store.data);
3688 addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 8, fr_src,
3698 IRType ty = typeOfIRExpr(env->type_env, stmt->Ist.Put.data);
3702 HReg r_src = iselWordExpr_R(env, stmt->Ist.Put.data);
3705 addInstr(env, MIPSInstr_Store(toUChar(sizeofIRType(ty)),
3716 iselInt64Expr(&vHi, &vLo, env, stmt->Ist.Put.data);
3717 addInstr(env, MIPSInstr_Store(toUChar(sizeofIRType(Ity_I32)),
3719 addInstr(env, MIPSInstr_Store(toUChar(sizeofIRType(Ity_I32)),
3726 HReg fr_src = iselFltExpr(env, stmt->Ist.Put.data);
3729 addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 4, fr_src,
3735 HReg fr_src = iselFltExpr(env, stmt->Ist.Put.data);
3738 addInstr(env, MIPSInstr_FpLdSt(False /*store */ , 8, fr_src,
3748 IRType ty = typeOfIRTemp(env->type_env, tmp);
3751 HReg r_dst = lookupIRTemp(env, tmp);
3752 HReg r_src = iselWordExpr_R(env, stmt->Ist.WrTmp.data);
3753 addInstr(env, mk_iMOVds_RR(r_dst, r_src));
3759 HReg r_dst = lookupIRTemp(env, tmp);
3760 HReg r_src = iselWordExpr_R(env, stmt->Ist.WrTmp.data);
3761 addInstr(env, mk_iMOVds_RR(r_dst, r_src));
3765 iselInt64Expr(&rHi, &rLo, env, stmt->Ist.WrTmp.data);
3766 lookupIRTemp64(&dstHi, &dstLo, env, tmp);
3767 addInstr(env, mk_iMOVds_RR(dstHi, rHi));
3768 addInstr(env, mk_iMOVds_RR(dstLo, rLo));
3775 iselInt128Expr(&rHi, &rLo, env, stmt->Ist.WrTmp.data);
3776 lookupIRTempPair(&dstHi, &dstLo, env, tmp);
3777 addInstr(env, mk_iMOVds_RR(dstHi, rHi));
3778 addInstr(env, mk_iMOVds_RR(dstLo, rLo));
3783 HReg fr_dst = lookupIRTemp(env, tmp);
3784 HReg fr_src = iselFltExpr(env, stmt->Ist.WrTmp.data);
3785 addInstr(env, MIPSInstr_FpUnary(Mfp_MOVS, fr_dst, fr_src));
3791 HReg src = iselFltExpr(env, stmt->Ist.WrTmp.data);
3792 HReg dst = lookupIRTemp(env, tmp);
3793 addInstr(env, MIPSInstr_FpUnary(Mfp_MOVD, dst, src));
3796 HReg src = iselDblExpr(env, stmt->Ist.WrTmp.data);
3797 HReg dst = lookupIRTemp(env, tmp);
3798 addInstr(env, MIPSInstr_FpUnary(Mfp_MOVD, dst, src));
3812 retty = typeOfIRTemp(env->type_env, d->tmp);
3833 doHelperCall( &addToSp, &rloc, env, d->guard, d->cee, retty, d->args );
3848 HReg r_dst = lookupIRTemp(env, d->tmp);
3849 addInstr(env, mk_iMOVds_RR(r_dst, hregMIPS_GPR2(mode64)));
3858 HReg r_dst = lookupIRTemp(env, d->tmp);
3859 addInstr(env, mk_iMOVds_RR(r_dst, hregMIPS_GPR2(mode64)));
3864 HReg rHi = newVRegI(env);
3865 HReg rLo = newVRegI(env);
3867 addInstr(env, mk_iMOVds_RR(rLo, hregMIPS_GPR2(mode64)));
3868 addInstr(env, mk_iMOVds_RR(rHi, hregMIPS_GPR3(mode64)));
3869 lookupIRTemp64(&dstHi, &dstLo, env, d->tmp);
3870 addInstr(env, mk_iMOVds_RR(dstHi, rHi));
3871 addInstr(env, mk_iMOVds_RR(dstLo, rLo));
3883 HReg dst = lookupIRTemp(env, d->tmp);
3885 addInstr(env, MIPSInstr_Load(mode64 ? 8 : 4, dst, am, mode64));
3886 add_to_sp(env, addToSp);
3903 IRType tyRes = typeOfIRTemp(env->type_env, res);
3904 IRType tyAddr = typeOfIRExpr(env->type_env, stmt->Ist.LLSC.addr);
3913 r_addr = iselWordExpr_AMode(env, stmt->Ist.LLSC.addr, tyAddr);
3915 HReg r_dst = lookupIRTemp(env, res);
3917 addInstr(env, MIPSInstr_LoadL(4, r_dst, r_addr, mode64));
3920 addInstr(env, MIPSInstr_LoadL(8, r_dst, r_addr, mode64));
3926 r_addr = iselWordExpr_AMode(env, stmt->Ist.LLSC.addr, tyAddr);
3927 HReg r_src = iselWordExpr_R(env, stmt->Ist.LLSC.storedata);
3928 HReg r_dst = lookupIRTemp(env, res);
3929 IRType tyData = typeOfIRExpr(env->type_env,
3933 addInstr(env, mk_iMOVds_RR(r_dst, r_src));
3934 addInstr(env, MIPSInstr_StoreC(4, r_addr, r_dst, mode64));
3937 addInstr(env, mk_iMOVds_RR(r_dst, r_src));
3938 addInstr(env, MIPSInstr_StoreC(8, r_addr, r_dst, mode64));
3948 HReg old = lookupIRTemp(env, cas->oldLo);
3949 HReg addr = iselWordExpr_R(env, cas->addr);
3950 HReg expd = iselWordExpr_R(env, cas->expdLo);
3951 HReg data = iselWordExpr_R(env, cas->dataLo);
3952 if (typeOfIRTemp(env->type_env, cas->oldLo) == Ity_I64) {
3953 addInstr(env, MIPSInstr_Cas(8, old, addr, expd, data, mode64));
3954 } else if (typeOfIRTemp(env->type_env, cas->oldLo) == Ity_I32) {
3955 addInstr(env, MIPSInstr_Cas(4, old, addr, expd, data, mode64));
3984 MIPSCondCode cc = iselCondCode(env, stmt->Ist.Exit.guard);
3992 if (env->chainingAllowed) {
3998 ? (((Addr64)stmt->Ist.Exit.dst->Ico.U64) > (Addr64)env->max_ga)
3999 : (((Addr32)stmt->Ist.Exit.dst->Ico.U32) > (Addr32)env->max_ga);
4001 addInstr(env, MIPSInstr_XDirect(
4009 HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
4010 addInstr(env, MIPSInstr_XAssisted(r, amPC, cc, Ijk_Boring));
4031 HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
4032 addInstr(env, MIPSInstr_XAssisted(r, amPC, cc,
4058 static void iselNext ( ISelEnv* env,
4072 vassert(cdst->tag == (env->mode64 ? Ico_U64 :Ico_U32));
4075 MIPSAMode* amPC = MIPSAMode_IR(offsIP, GuestStatePointer(env->mode64));
4076 if (env->chainingAllowed) {
4081 = env->mode64
4082 ? (((Addr64)cdst->Ico.U64) > (Addr64)env->max_ga)
4083 : (((Addr32)cdst->Ico.U32) > (Addr32)env->max_ga);
4085 addInstr(env, MIPSInstr_XDirect(
4086 env->mode64 ? (Addr64)cdst->Ico.U64
4093 HReg r = iselWordExpr_R(env, next);
4094 addInstr(env, MIPSInstr_XAssisted(r, amPC, MIPScc_AL,
4104 HReg r = iselWordExpr_R(env, next);
4106 GuestStatePointer(env->mode64));
4107 if (env->chainingAllowed) {
4108 addInstr(env, MIPSInstr_XIndir(r, amPC, MIPScc_AL));
4110 addInstr(env, MIPSInstr_XAssisted(r, amPC, MIPScc_AL,
4134 HReg r = iselWordExpr_R(env, next);
4135 MIPSAMode* amPC = MIPSAMode_IR(offsIP, GuestStatePointer(env->mode64));
4136 addInstr(env, MIPSInstr_XAssisted(r, amPC, MIPScc_AL, jk));
4168 ISelEnv* env;
4189 env = LibVEX_Alloc_inline(sizeof(ISelEnv));
4190 env->vreg_ctr = 0;
4191 env->mode64 = mode64;
4192 env->fp_mode64 = fp_mode64;
4195 env->code = newHInstrArray();
4197 /* Copy BB's type env. */
4198 env->type_env = bb->tyenv;
4202 env->n_vregmap = bb->tyenv->types_used;
4203 env->vregmap = LibVEX_Alloc_inline(env->n_vregmap * sizeof(HReg));
4204 env->vregmapHI = LibVEX_Alloc_inline(env->n_vregmap * sizeof(HReg));
4207 env->hwcaps = hwcaps_host;
4208 env->chainingAllowed = chainingAllowed;
4209 env->hwcaps = hwcaps_host;
4210 env->max_ga = max_ga;
4215 for (i = 0; i < env->n_vregmap; i++) {
4259 env->vregmap[i] = hreg;
4260 env->vregmapHI[i] = hregHI;
4262 env->vreg_ctr = j;
4267 addInstr(env, MIPSInstr_EvCheck(amCounter, amFailAddr));
4274 addInstr(env, MIPSInstr_ProfInc());
4279 iselStmt(env, bb->stmts[i]);
4281 iselNext(env, bb->next, bb->jumpkind, bb->offsIP);
4284 env->code->n_vregs = env->vreg_ctr;
4285 return env->code;
