Lines Matching refs:mode64
53 static Bool mode64 = False;
121 Bool mode64;
152 vassert(env->mode64);
164 ppMIPSInstr(instr, mode64);
172 HRcGPR(env->mode64), 0/*enc*/, env->vreg_ctr);
188 HRcFPR(env->mode64), 0/*enc*/, env->vreg_ctr);
195 HReg sp = StackPointer(mode64);
197 if (mode64)
207 HReg sp = StackPointer(mode64);
209 if (mode64)
297 am_addr = MIPSAMode_IR(0, StackPointer(mode64));
300 addInstr(env, MIPSInstr_Store(4, am_addr, fcsr_old, mode64));
311 am_addr = MIPSAMode_IR(0, StackPointer(mode64));
313 addInstr(env, MIPSInstr_Load(4, fcsr, am_addr, mode64));
364 am_addr0 = MIPSAMode_IR(0, StackPointer(mode64));
365 am_addr1 = MIPSAMode_IR(4, StackPointer(mode64));
369 addInstr(env, MIPSInstr_Store(4, am_addr0, r_srcLo, mode64));
370 addInstr(env, MIPSInstr_Store(4, am_addr1, r_srcHi, mode64));
372 addInstr(env, MIPSInstr_Store(4, am_addr0, r_srcHi, mode64));
373 addInstr(env, MIPSInstr_Store(4, am_addr1, r_srcLo, mode64));
455 if (mode64) {
456 argregs[0] = hregMIPS_GPR4(mode64);
457 argregs[1] = hregMIPS_GPR5(mode64);
458 argregs[2] = hregMIPS_GPR6(mode64);
459 argregs[3] = hregMIPS_GPR7(mode64);
460 argregs[4] = hregMIPS_GPR8(mode64);
461 argregs[5] = hregMIPS_GPR9(mode64);
462 argregs[6] = hregMIPS_GPR10(mode64);
463 argregs[7] = hregMIPS_GPR11(mode64);
469 argregs[0] = hregMIPS_GPR4(mode64);
470 argregs[1] = hregMIPS_GPR5(mode64
471 argregs[2] = hregMIPS_GPR6(mode64);
472 argregs[3] = hregMIPS_GPR7(mode64);
521 if (aTy == Ity_I32 || mode64) {
541 GuestStatePointer(mode64)));
562 if (aTy == Ity_I32 || (mode64 && arg->tag != Iex_BBPTR)) {
577 tmpregs[argreg] = GuestStatePointer(mode64);
623 *retloc = mk_RetLoc_simple(mode64 ? RLPri_Int : RLPri_2Int);
644 Addr64 target = mode64 ? (Addr)cee->addr :
692 return toBool(hregClass(am->Mam.IR.base) == HRcGPR(mode64) &&
696 return toBool(hregClass(am->Mam.RR.base) == HRcGPR(mode64) &&
698 hregClass(am->Mam.RR.index) == HRcGPR(mode64) &&
717 if (env->mode64) {
778 All results are returned in a (mode64 ? 64bit : 32bit) register.
788 vassert(hregClass(r) == HRcGPR(env->mode64));
799 || ty == Ity_F32 || (ty == Ity_I64 && mode64)
800 || (ty == Ity_I128 && mode64));
817 r_dst, am_addr, mode64));
926 if (mode64)
934 if (mode64 && (shftOp == Mshft_SRA || shftOp == Mshft_SRL)) {
955 vassert(mode64);
1115 if (mode64) {
1262 vassert(mode64);
1283 vassert(mode64);
1302 if (mode64)
1343 rloc = mode64 ? mk_RetLoc_simple(RLPri_Int) :
1354 addInstr(env, mk_iMOVds_RR(hregMIPS_GPR4(env->mode64), regL));
1355 addInstr(env, mk_iMOVds_RR(hregMIPS_GPR5(env->mode64), regR));
1361 addInstr(env, mk_iMOVds_RR(res, hregMIPS_GPR2(env->mode64)));
1468 vassert(mode64);
1481 if (mode64)
1515 vassert(mode64);
1546 vassert(mode64);
1552 vassert(mode64);
1558 vassert(mode64);
1574 vassert(mode64);
1583 if (env->mode64) {
1597 if (env->mode64) {
1609 vassert(env->mode64);
1618 vassert(mode64);
1634 hregMIPS_GPR0(mode64), MIPScc_NE));
1643 hregMIPS_GPR0(mode64), MIPScc_NE));
1651 addInstr(env, MIPSInstr_Alu(Malu_SUB, r_dst, hregMIPS_GPR0(mode64),
1665 if (op_unop == Iop_Left64 && !mode64)
1671 hregMIPS_GPR0(mode64),
1679 vassert(mode64);
1692 if (env->mode64) {
1699 addInstr(env, MIPSInstr_Cmp(False, !(env->mode64), r_dst, r_src,
1700 hregMIPS_GPR0(mode64), MIPScc_NE));
1707 vassert(env->mode64);
1710 addInstr(env, MIPSInstr_Alu(Malu_DSUB, tmp2, hregMIPS_GPR0(mode64),
1720 vassert(mode64);
1727 vassert(mode64);
1754 rloc = mode64 ? mk_RetLoc_simple(RLPri_Int) :
1764 addInstr(env, mk_iMOVds_RR(hregMIPS_GPR4(env->mode64), regL));
1769 addInstr(env, mk_iMOVds_RR(res, hregMIPS_GPR2(env->mode64)));
1779 || ((ty == Ity_I64) && mode64)) {
1783 GuestStatePointer(mode64));
1785 mode64));
1817 if (!mode64)
1857 addInstr(env, mk_iMOVds_RR(r_dst, hregMIPS_GPR2(mode64)));
1895 vassert(hregClass(ri->Mrh.Reg.reg) == HRcGPR(env->mode64));
1910 ((ty == Ity_I64) && env->mode64));
1919 vassert(env->mode64);
2004 vassert(hregClass(ri->Mrh.Reg.reg) == HRcGPR(env->mode64));
2124 MIPSAMode *am_addr = MIPSAMode_IR(0, GuestStatePointer(mode64));
2127 MIPSAMode_IR(am_addr->Mam.IR.index + COND_OFFSET(mode64),
2129 dst, mode64));
2140 MIPSAMode *am_addr = MIPSAMode_IR(0, GuestStatePointer(mode64));
2143 MIPSAMode_IR(am_addr->Mam.IR.index + COND_OFFSET(mode64),
2145 r_dst, mode64));
2151 MIPSAMode *am_addr = MIPSAMode_IR(0, GuestStatePointer(mode64));
2154 MIPSAMode_IR(am_addr->Mam.IR.index + COND_OFFSET(mode64),
2156 r_dst, mode64));
2177 vassert(env->mode64);
2179 vassert(hregClass(*rHi) == HRcGPR(env->mode64));
2181 vassert(hregClass(*rLo) == HRcGPR(env->mode64));
2242 vassert(mode64);
2278 vassert(!env->mode64);
2302 addInstr(env, MIPSInstr_Load(4, tHi, MIPSAMode_IR(0, r_addr), mode64));
2303 addInstr(env, MIPSInstr_Load(4, tLo, MIPSAMode_IR(4, r_addr), mode64));
2339 GuestStatePointer(mode64));
2340 addInstr(env, MIPSInstr_Load(4, tLo, am_addr, mode64));
2341 addInstr(env, MIPSInstr_Load(4, tHi, nextMIPSAModeInt(am_addr), mode64));
2777 am_addr = MIPSAMode_IR(0, StackPointer(mode64));
2784 addInstr(env, MIPSInstr_Load(4, tLo, am_addr, mode64));
2786 mode64));
2788 addInstr(env, MIPSInstr_Load(4, tHi, am_addr, mode64));
2790 mode64));
2850 addInstr(env, MIPSInstr_Alu(Malu_ADD, tHi, hregMIPS_GPR0(mode64),
2851 MIPSRH_Reg(hregMIPS_GPR0(mode64))));
2863 addInstr(env, MIPSInstr_Alu(Malu_ADD, tHi, hregMIPS_GPR0(mode64),
2864 MIPSRH_Reg(hregMIPS_GPR0(mode64))));
2912 addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp2, hregMIPS_GPR0(mode64),
2930 am_addr = MIPSAMode_IR(0, StackPointer(mode64));
2937 addInstr(env, MIPSInstr_Load(4, tLo, am_addr, mode64));
2939 mode64));
2941 addInstr(env, MIPSInstr_Load(4, tHi, am_addr, mode64));
2943 mode64));
3007 GuestStatePointer(mode64));
3041 if (mode64) {
3087 vassert(mode64);
3094 vassert(mode64);
3101 vassert(mode64);
3108 vassert(mode64);
3180 if (mode64)
3232 if (mode64) {
3237 am_addr = MIPSAMode_IR(0, StackPointer(mode64));
3240 addInstr(env, MIPSInstr_Store(8, am_addr, fr_src, mode64));
3265 if (mode64) {
3270 am_addr = MIPSAMode_IR(0, StackPointer(mode64));
3273 addInstr(env, MIPSInstr_Store(8, am_addr, fr_src, mode64));
3381 MIPSAMode *zero_r1 = MIPSAMode_IR(0, StackPointer(mode64));
3396 vassert(mode64);
3447 GuestStatePointer(mode64));
3462 vassert(!mode64);
3479 vassert(!mode64);
3656 (mode64 && (tyd == Ity_I64))) {
3659 am_addr, r_src, mode64));
3662 if (!mode64 && (tyd == Ity_I64)) {
3669 MIPSAMode_IR(0, r_addr), vHi, mode64));
3671 MIPSAMode_IR(4, r_addr), vLo, mode64));
3680 if (tyd == Ity_F64 && mode64) {
3686 if (!mode64 && (tyd == Ity_F64)) {
3701 (ty == Ity_I64 && mode64)) {
3704 GuestStatePointer(mode64));
3706 am_addr, r_src, mode64));
3710 if (ty == Ity_I64 && !mode64) {
3713 GuestStatePointer(mode64));
3715 GuestStatePointer(mode64));
3718 am_addr, vLo, mode64));
3720 am_addr4, vHi, mode64));
3728 GuestStatePointer(mode64));
3737 mode64));
3758 if (mode64) {
3773 if (mode64 && ty == Ity_I128) {
3790 if (mode64) {
3849 addInstr(env, mk_iMOVds_RR(r_dst, hregMIPS_GPR2(mode64)));
3855 if (mode64) {
3859 addInstr(env, mk_iMOVds_RR(r_dst, hregMIPS_GPR2(mode64)));
3867 addInstr(env, mk_iMOVds_RR(rLo, hregMIPS_GPR2(mode64)));
3868 addInstr(env, mk_iMOVds_RR(rHi, hregMIPS_GPR3(mode64)));
3884 MIPSAMode* am = MIPSAMode_IR(rloc.spOff, StackPointer(mode64));
3885 addInstr(env, MIPSInstr_Load(mode64 ? 8 : 4, dst, am, mode64));
3906 if (!mode64 && (tyAddr != Ity_I32))
3917 addInstr(env, MIPSInstr_LoadL(4, r_dst, r_addr, mode64));
3919 } else if (tyRes == Ity_I64 && mode64) {
3920 addInstr(env, MIPSInstr_LoadL(8, r_dst, r_addr, mode64));
3934 addInstr(env, MIPSInstr_StoreC(4, r_addr, r_dst, mode64));
3936 } else if (tyData == Ity_I64 && mode64) {
3938 addInstr(env, MIPSInstr_StoreC(8, r_addr, r_dst, mode64));
3953 addInstr(env, MIPSInstr_Cas(8, old, addr, expd, data, mode64));
3955 addInstr(env, MIPSInstr_Cas(4, old, addr, expd, data, mode64));
3979 if (!mode64 && dst->tag != Ico_U32)
3981 if (mode64 && dst->tag != Ico_U64)
3986 GuestStatePointer(mode64));
3997 = mode64
4002 mode64 ? (Addr64)stmt->Ist.Exit.dst->Ico.U64
4072 vassert(cdst->tag == (env->mode64 ? Ico_U64 :Ico_U32));
4075 MIPSAMode* amPC = MIPSAMode_IR(offsIP, GuestStatePointer(env->mode64));
4081 = env->mode64
4086 env->mode64 ? (Addr64)cdst->Ico.U64
4106 GuestStatePointer(env->mode64));
4135 MIPSAMode* amPC = MIPSAMode_IR(offsIP, GuestStatePointer(env->mode64));
4182 mode64 = arch_host != VexArchMIPS32;
4191 env->mode64 = mode64;
4222 if (mode64) {
4230 if (mode64) {
4239 vassert(mode64);
4244 if (mode64) {
4265 amCounter = MIPSAMode_IR(offs_Host_EvC_Counter, GuestStatePointer(mode64));
4266 amFailAddr = MIPSAMode_IR(offs_Host_EvC_FailAddr, GuestStatePointer(mode64));
