Lines Matching defs:env
61 GPR11 if mode64: not used - calls by ptr / env ptr for some langs
302 static HReg lookupIRTemp ( ISelEnv* env, IRTemp tmp )
305 vassert(tmp < env->n_vregmap);
306 return env->vregmapLo[tmp];
310 ISelEnv* env, IRTemp tmp )
313 vassert(tmp < env->n_vregmap);
314 vassert(! hregIsInvalid(env->vregmapMedLo[tmp]));
315 *vrLO = env->vregmapLo[tmp];
316 *vrHI = env->vregmapMedLo[tmp];
321 HReg* vrLo, ISelEnv* env, IRTemp tmp )
323 vassert(!env->mode64);
325 vassert(tmp < env->n_vregmap);
326 vassert(! hregIsInvalid(env->vregmapMedLo[tmp]));
327 *vrHi = env->vregmapHi[tmp];
328 *vrMedHi = env->vregmapMedHi[tmp];
329 *vrMedLo = env->vregmapMedLo[tmp];
330 *vrLo = env->vregmapLo[tmp];
333 static void addInstr ( ISelEnv* env, PPCInstr* instr )
335 addHInstr(env->code, instr);
337 ppPPCInstr(instr, env->mode64);
342 static HReg newVRegI ( ISelEnv* env )
345 = mkHReg(True/*vreg*/, HRcGPR(env->mode64), 0/*enc*/, env->vreg_ctr);
346 env->vreg_ctr++;
350 static HReg newVRegF ( ISelEnv* env )
352 HReg reg = mkHReg(True/*vreg*/, HRcFlt64, 0/*enc*/, env->vreg_ctr);
353 env->vreg_ctr++;
357 static HReg newVRegV ( ISelEnv* env )
359 HReg reg = mkHReg(True/*vreg*/, HRcVec128, 0/*enc*/, env->vreg_ctr);
360 env->vreg_ctr++;
382 static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e,
384 static HReg iselWordExpr_R ( ISelEnv* env, IRExpr* e,
396 static PPCRH* iselWordExpr_RH_wrk ( ISelEnv* env,
399 static PPCRH* iselWordExpr_RH ( ISelEnv* env,
405 static PPCRI* iselWordExpr_RI_wrk ( ISelEnv* env, IRExpr* e,
407 static PPCRI* iselWordExpr_RI ( ISelEnv* env, IRExpr* e,
413 static PPCRH* iselWordExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e,
415 static PPCRH* iselWordExpr_RH5u ( ISelEnv* env, IRExpr* e,
421 static PPCRH* iselWordExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e,
423 static PPCRH* iselWordExpr_RH6u ( ISelEnv* env, IRExpr* e,
437 static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env
440 static PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e,
446 ISelEnv* env, IRExpr* e,
450 ISelEnv* env, IRExpr* e,
456 ISelEnv* env, IRExpr* e,
459 ISelEnv* env, IRExpr* e,
464 ISelEnv* env, IRExpr* e,
468 ISelEnv* env, IRExpr* e,
471 static PPCCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e,
473 static PPCCondCode iselCondCode ( ISelEnv* env, IRExpr* e,
476 static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e,
478 static HReg iselDblExpr ( ISelEnv* env, IRExpr* e,
481 static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e,
483 static HReg iselFltExpr ( ISelEnv* env, IRExpr* e,
486 static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e,
488 static HReg iselVecExpr ( ISelEnv* env, IRExpr* e,
492 static HReg iselDfp32Expr_wrk ( ISelEnv* env, IRExpr* e,
494 static HReg iselDfp32Expr ( ISelEnv* env, IRExpr* e,
496 static HReg iselDfp64Expr_wrk ( ISelEnv* env, IRExpr* e,
498 static HReg iselDfp64Expr ( ISelEnv* env, IRExpr* e,
502 static void iselDfp128Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env,
504 static void iselDfp128Expr ( HReg* rHi, HReg* rLo, ISelEnv* env,
523 static void add_to_sp ( ISelEnv* env, UInt n )
525 HReg sp = StackFramePtr(env->mode64);
527 addInstr(env, PPCInstr_Alu( Palu_ADD, sp, sp,
531 static void sub_from_sp ( ISelEnv* env, UInt n )
533 HReg sp = StackFramePtr(env->mode64);
535 addInstr(env, PPCInstr_Alu( Palu_SUB, sp, sp,
545 static HReg get_sp_aligned16 ( ISelEnv* env )
547 HReg r = newVRegI(env);
548 HReg align16 = newVRegI(env);
549 addInstr(env, mk_iMOVds_RR(r, StackFramePtr(env->mode64)));
551 addInstr(env, PPCInstr_Alu( Palu_ADD, r, r,
554 addInstr(env,
555 PPCInstr_LI(align16, 0xFFFFFFFFFFFFFFF0ULL, env->mode64));
556 addInstr(env, PPCInstr_Alu(Palu_AND, r,r, PPCRH_Reg(align16)));
563 static HReg mk_LoadRR32toFPR ( ISelEnv* env,
566 HReg fr_dst = newVRegF(env);
569 vassert(!env->mode64);
573 sub_from_sp( env, 16 ); // Move SP down 16 bytes
574 am_addr0 = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
575 am_addr1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) );
578 addInstr(env, PPCInstr_Store( 4, am_addr0, r_srcHi, env->mode64 ));
579 addInstr(env, PPCInstr_Store( 4, am_addr1, r_srcLo, env->mode64 ));
582 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fr_dst, am_addr0));
584 add_to_sp( env, 16 ); // Reset SP
589 static HReg mk_LoadR64toFPR ( ISelEnv* env, HReg r_src )
591 HReg fr_dst = newVRegF(env);
594 vassert(env->mode64);
597 sub_from_sp( env, 16 ); // Move SP down 16 bytes
598 am_addr0 = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
601 addInstr(env, PPCInstr_Store( 8, am_addr0, r_src, env->mode64 ));
604 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fr_dst, am_addr0));
606 add_to_sp( env, 16 ); // Reset SP
614 static PPCAMode* advance4 ( ISelEnv* env, PPCAMode* am )
631 PPCAMode* genGuestArrayOffset ( ISelEnv* env, IRRegArray* descr,
664 roff = iselWordExpr_R(env, off, IEndianess);
665 rtmp = newVRegI(env);
666 addInstr(env, PPCInstr_Alu(
670 addInstr(env, PPCInstr_Alu(
674 addInstr(env, PPCInstr_Shft(
676 env->mode64 ? False : True/*F:64-bit, T:32-bit shift*/,
679 addInstr(env, PPCInstr_Alu(
684 PPCAMode_RR( GuestStatePtr(env->mode64), rtmp );
719 ISelEnv* env,
730 Bool mode64 = env->mode64;
883 addInstr(env, mk_iMOVds_RR( argregs[argreg],
888 IRType ty = typeOfIRExpr(env->type_env, arg);
893 addInstr(env,
895 iselWordExpr_R(env, arg,
903 iselInt64Expr(&rHi,&rLo, env, arg, IEndianess);
905 addInstr(env, mk_iMOVds_RR( argregs[argreg++], rHi ));
907 addInstr(env, mk_iMOVds_RR( argregs[argreg], rLo));
911 addInstr(env, mk_iMOVds_RR( argregs[argreg],
912 iselWordExpr_R(env, arg,
938 r_vecRetAddr = newVRegI(env);
939 sub_from_sp(env, 512);
940 addInstr(env, mk_iMOVds_RR( r_vecRetAddr, StackFramePtr(mode64) ));
941 sub_from_sp(env, 512);
945 r_vecRetAddr = newVRegI(env);
946 sub_from_sp(env, 512);
947 addInstr(env, mk_iMOVds_RR( r_vecRetAddr, StackFramePtr(mode64) ));
948 sub_from_sp(env, 512);
956 tmpregs[argreg] = newVRegI(env);
957 addInstr(env, mk_iMOVds_RR( tmpregs[argreg],
969 IRType ty = typeOfIRExpr(env->type_env, arg);
973 tmpregs[argreg] = iselWordExpr_R(env, arg, IEndianess);
980 iselInt64Expr(&rHi,&rLo, env, arg, IEndianess);
985 tmpregs[argreg] = iselWordExpr_R(env, arg, IEndianess);
1002 cc = iselCondCode( env, guard, IEndianess );
1013 addInstr( env, mk_iMOVds_RR( argregs[i], tmpregs[i] ) );
1064 addInstr(env, PPCInstr_Call( cc, target, argiregs, *retloc ));
1074 //void set_FPU_rounding_default ( ISelEnv* env )
1076 // HReg fr_src = newVRegF(env);
1077 // HReg r_src = newVRegI(env);
1084 // addInstr(env, PPCInstr_LI(r_src, 0x0, env->mode64));
1085 // if (env->mode64) {
1086 // fr_src = mk_LoadR64toFPR( env, r_src ); // 1*I64 -> F64
1088 // fr_src = mk_LoadRR32toFPR( env, r_src, r_src ); // 2*I32 -> F64
1090 // addInstr(env, PPCInstr_FpLdFPSCR( fr_src ));
1094 static HReg roundModeIRtoPPC ( ISelEnv* env, HReg r_rmIR )
1109 HReg r_rmPPC = newVRegI(env);
1110 HReg r_tmp1 = newVRegI(env);
1111 HReg r_tmp2 = newVRegI(env);
1113 vassert(hregClass(r_rmIR) == HRcGPR(env->mode64));
1121 addInstr(env, PPCInstr_Shft(Pshft_SHL, True/*32bit shift*/,
1124 addInstr( env, PPCInstr_Alu( Palu_AND,
1127 addInstr( env, PPCInstr_Alu( Palu_XOR,
1147 env->previous_rm.) If 'mode' is a single IR temporary 't' and
1148 env->previous_rm is also just 't', then the setting is skipped.
1164 void _set_FPU_rounding_mode ( ISelEnv* env, IRExpr* mode, Bool dfp_rm,
1167 HReg fr_src = newVRegF(env);
1170 vassert(typeOfIRExpr(env->type_env,mode) == Ity_I32);
1173 if (env->previous_rm
1174 && env->previous_rm->tag == Iex_RdTmp
1176 && env->previous_rm->Iex.RdTmp.tmp == mode->Iex.RdTmp.tmp) {
1178 vassert(typeOfIRExpr(env->type_env, env->previous_rm) == Ity_I32);
1183 env->previous_rm = mode;
1189 r_src = roundModeIRtoPPC( env, iselWordExpr_R(env, mode, IEndianess) );
1192 if (env->mode64) {
1194 HReg r_tmp1 = newVRegI( env );
1195 addInstr( env,
1198 fr_src = mk_LoadR64toFPR( env, r_tmp1 );
1200 fr_src = mk_LoadR64toFPR( env, r_src ); // 1*I64 -> F64
1204 HReg r_zero = newVRegI( env );
1205 addInstr( env, PPCInstr_LI( r_zero, 0, env->mode64 ) );
1206 fr_src = mk_LoadRR32toFPR( env, r_src, r_zero );
1208 fr_src = mk_LoadRR32toFPR( env, r_src, r_src ); // 2*I32 -> F64
1213 addInstr(env, PPCInstr_FpLdFPSCR( fr_src, dfp_rm ));
1216 static void set_FPU_rounding_mode ( ISelEnv* env, IRExpr* mode,
1219 _set_FPU_rounding_mode(env, mode, False, IEndianess);
1222 static void set_FPU_DFP_rounding_mode ( ISelEnv* env, IRExpr* mode,
1225 _set_FPU_rounding_mode(env, mode, True, IEndianess);
1235 static HReg generate_zeroes_V128 ( ISelEnv* env )
1237 HReg dst = newVRegV(env);
1238 addInstr(env, PPCInstr_AvBinary(Pav_XOR, dst, dst, dst));
1244 static HReg generate_ones_V128 ( ISelEnv* env )
1246 HReg dst = newVRegV(env);
1248 addInstr(env, PPCInstr_AvSplat(8, dst, src));
1260 static HReg mk_AvDuplicateRI( ISelEnv* env, IRExpr* e, IREndness IEndianess )
1263 HReg dst = newVRegV(env);
1264 PPCRI* ri = iselWordExpr_RI(env, e, IEndianess);
1265 IRType ty = typeOfIRExpr(env->type_env,e);
1277 HReg v1 = newVRegV(env);
1278 HReg v2 = newVRegV(env);
1279 addInstr(env, PPCInstr_AvSplat(sz, v1, PPCVI5s_Imm(-16)));
1280 addInstr(env, PPCInstr_AvSplat(sz, v2, PPCVI5s_Imm(simm6-16)));
1281 addInstr(env,
1288 HReg v1 = newVRegV(env);
1289 HReg v2 = newVRegV(env);
1290 addInstr(env, PPCInstr_AvSplat(sz, v1, PPCVI5s_Imm(-16)));
1291 addInstr(env, PPCInstr_AvSplat(sz, v2, PPCVI5s_Imm(simm6+16)));
1292 addInstr(env,
1299 addInstr(env, PPCInstr_AvSplat(sz, dst, PPCVI5s_Imm(simm6)));
1304 r_src = newVRegI(env);
1305 addInstr(env, PPCInstr_LI(r_src, (Long)simm32, env->mode64));
1316 sub_from_sp( env, 32 ); // Move SP down
1318 r_aligned16 = get_sp_aligned16( env );
1326 addInstr(env, PPCInstr_Store( num_bytes_to_store, am_offset, r_src, env->mode64 ));
1330 addInstr(env, PPCInstr_AvLdSt( True/*ld*/, 16, dst, am_offset_zero ) );
1331 add_to_sp( env, 32 ); // Reset SP
1339 static HReg isNan ( ISelEnv* env, HReg vSrc, IREndness IEndianess )
1345 zeros = mk_AvDuplicateRI(env, mkU32(0), IEndianess);
1346 msk_exp = mk_AvDuplicateRI(env, mkU32(0x7F800000), IEndianess);
1347 msk_mnt = mk_AvDuplicateRI(env, mkU32(0x7FFFFF), IEndianess);
1348 expt = newVRegV(env);
1349 mnts = newVRegV(env);
1350 vIsNan = newVRegV(env);
1355 addInstr(env, PPCInstr_AvBinary(Pav_AND, expt, vSrc, msk_exp));
1356 addInstr(env, PPCInstr_AvBin32x4(Pav_CMPEQU, expt, expt, msk_exp));
1357 addInstr(env, PPCInstr_AvBinary(Pav_AND, mnts, vSrc, msk_mnt));
1358 addInstr(env, PPCInstr_AvBin32x4(Pav_CMPGTU, mnts, mnts, zeros));
1359 addInstr(env, PPCInstr_AvBinary(Pav_AND, vIsNan, expt, mnts));
1383 static HReg iselWordExpr_R ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
1385 HReg r = iselWordExpr_R_wrk(env, e, IEndianess);
1391 vassert(hregClass(r) == HRcGPR(env->mode64));
1397 static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e,
1400 Bool mode64 = env->mode64;
1404 IRType ty = typeOfIRExpr(env->type_env,e);
1412 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
1420 r_dst = newVRegI(env);
1421 am_addr = iselWordExpr_AMode( env, e->Iex.Load.addr, ty/*of xfer*/,
1423 addInstr(env, PPCInstr_Load( toUChar(sizeofIRType(ty)),
1452 HReg r_dst = newVRegI(env);
1453 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1458 ri_srcR = iselWordExpr_RH(env, True/*signed*/,
1462 ri_srcR = iselWordExpr_RH(env, False/*signed*/,
1468 addInstr(env, PPCInstr_Alu(aluOp, r_dst, r_srcL, ri_srcR));
1485 HReg r_dst = newVRegI(env);
1486 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1492 ri_srcR = iselWordExpr_RH5u(env, e->Iex.Binop.arg2, IEndianess);
1494 ri_srcR = iselWordExpr_RH6u(env, e->Iex.Binop.arg2, IEndianess);
1504 HReg tmp = newVRegI(env);
1505 addInstr(env, PPCInstr_Shft(Pshft_SHL,
1508 addInstr(env, PPCInstr_Shft(shftOp,
1519 addInstr(env, PPCInstr_Shft(shftOp, False/*64bit shift*/,
1522 addInstr(env, PPCInstr_Shft(shftOp, True/*32bit shift*/,
1534 HReg r_dst = newVRegI(env);
1535 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1536 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
1537 addInstr( env,
1552 HReg r_dst = newVRegI(env);
1553 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1554 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
1556 addInstr( env,
1574 HReg r_dst = newVRegI(env);
1575 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1576 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
1577 addInstr(env, PPCInstr_MulL(syned, False/*lo32*/, sz32,
1586 HReg tLo = newVRegI(env);
1587 HReg tHi = newVRegI(env);
1588 HReg r_dst = newVRegI(env);
1590 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1591 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
1592 addInstr(env, PPCInstr_MulL(False/*signedness irrelevant*/,
1595 addInstr(env, PPCInstr_MulL(syned,
1598 addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64bit shift*/,
1600 addInstr(env, PPCInstr_Alu(Palu_OR,
1609 HReg dst = newVRegI(env);
1610 HReg srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1611 PPCRH* srcR = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2,
1613 addInstr(env, PPCInstr_Cmp(syned, True/*32bit cmp*/,
1615 addInstr(env, PPCInstr_MfCR(dst));
1616 addInstr(env, PPCInstr_Alu(Palu_AND, dst, dst,
1624 HReg dst = newVRegI(env);
1625 HReg srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1626 PPCRH* srcR = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2,
1629 addInstr(env, PPCInstr_Cmp(syned, False/*64bit cmp*/,
1631 addInstr(env, PPCInstr_MfCR(dst));
1632 addInstr(env, PPCInstr_Alu(Palu_AND, dst, dst,
1638 HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1639 HReg r2 = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
1640 HReg rdst = newVRegI(env);
1642 addInstr(env, mk_iMOVds_RR(rdst, r1));
1643 addInstr(env, PPCInstr_Cmp(False/*unsigned*/, True/*32bit cmp*/,
1645 addInstr(env, PPCInstr_CMov(cc, rdst, PPCRI_Reg(r2)));
1650 HReg r_Hi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1651 HReg r_Lo = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
1652 HReg r_Tmp = newVRegI(env);
1653 HReg r_dst = newVRegI(env);
1654 HReg msk = newVRegI(env);
1657 addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64bit shift*/,
1659 addInstr(env, PPCInstr_LI(msk, 0xFFFFFFFF, mode64));
1660 addInstr(env, PPCInstr_Alu( Palu_AND, r_Tmp, r_Lo,
1662 addInstr(env, PPCInstr_Alu( Palu_OR, r_dst, r_dst,
1675 HReg r_ccPPC = newVRegI(env);
1676 HReg r_ccIR = newVRegI(env);
1677 HReg r_ccIR_b0 = newVRegI(env);
1678 HReg r_ccIR_b2 = newVRegI(env);
1679 HReg r_ccIR_b6 = newVRegI(env);
1682 fr_srcL = iselDblExpr(env, e->Iex.Binop.arg1, IEndianess);
1683 fr_srcR = iselDblExpr(env, e->Iex.Binop.arg2, IEndianess);
1684 addInstr(env, PPCInstr_FpCmp(r_ccPPC, fr_srcL, fr_srcR));
1687 fr_srcL = iselDfp64Expr(env, e->Iex.Binop.arg1, IEndianess);
1688 fr_srcR = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess);
1689 addInstr(env, PPCInstr_Dfp64Cmp(r_ccPPC, fr_srcL, fr_srcR));
1692 iselDfp128Expr(&fr_srcL, &fr_srcL_lo, env, e->Iex.Binop.arg1,
1694 iselDfp128Expr(&fr_srcR, &fr_srcR_lo, env, e->Iex.Binop.arg2,
1696 addInstr(env, PPCInstr_Dfp128Cmp(r_ccPPC, fr_srcL, fr_srcL_lo,
1712 addInstr(env, PPCInstr_Shft(Pshft_SHR, True/*32bit shift*/,
1715 addInstr(env, PPCInstr_Alu(Palu_OR, r_ccIR_b0,
1717 addInstr(env, PPCInstr_Alu(Palu_AND, r_ccIR_b0,
1721 addInstr(env, PPCInstr_Shft(Pshft_SHL, True/*32bit shift*/,
1724 addInstr(env, PPCInstr_Alu(Palu_AND, r_ccIR_b2,
1728 addInstr(env, PPCInstr_Shft(Pshft_SHR, True/*32bit shift*/,
1731 addInstr(env, PPCInstr_Alu(Palu_OR, r_ccIR_b6,
1733 addInstr(env, PPCInstr_Shft(Pshft_SHL, True/*32bit shift*/,
1736 addInstr(env, PPCInstr_Alu(Palu_AND, r_ccIR_b6,
1740 addInstr(env, PPCInstr_Alu(Palu_OR, r_ccIR,
1742 addInstr(env, PPCInstr_Alu(Palu_OR, r_ccIR,
1750 HReg r1 = StackFramePtr(env->mode64);
1752 HReg fsrc = iselDblExpr(env, e->Iex.Binop.arg2, IEndianess);
1753 HReg ftmp = newVRegF(env);
1754 HReg idst = newVRegI(env);
1757 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
1759 sub_from_sp( env, 16 );
1760 addInstr(env, PPCInstr_FpCftI(False/*F->I*/, True/*int32*/,
1765 addInstr(env, PPCInstr_FpSTFIW(r1, ftmp));
1766 addInstr(env, PPCInstr_Load(4, idst, zero_r1, mode64));
1770 addInstr(env, PPCInstr_Unary(Pun_EXTSW, idst, idst));
1772 add_to_sp( env, 16 );
1775 //set_FPU_rounding_default( env );
1781 HReg r1 = StackFramePtr(env->mode64);
1783 HReg fsrc = iselDblExpr(env, e->Iex.Binop.arg2,
1785 HReg idst = newVRegI(env);
1786 HReg ftmp = newVRegF(env);
1789 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
1791 sub_from_sp( env, 16 );
1792 addInstr(env, PPCInstr_FpCftI(False/*F->I*/, False/*int64*/,
1796 addInstr(env, PPCInstr_FpLdSt(False/*store*/, 8, ftmp, zero_r1));
1797 addInstr(env, PPCInstr_Load(8, idst, zero_r1, True/*mode64*/));
1798 add_to_sp( env, 16 );
1801 //set_FPU_rounding_default( env );
1807 HReg r1 = StackFramePtr(env->mode64);
1809 HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess);
1810 HReg idst = newVRegI(env);
1811 HReg ftmp = newVRegF(env);
1814 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
1815 addInstr(env, PPCInstr_Dfp64Unary(Pfp_DCTFIX, ftmp, fr_src));
1816 sub_from_sp( env, 16 );
1817 addInstr(env, PPCInstr_FpLdSt(False/*store*/, 8, ftmp, zero_r1));
1818 addInstr(env, PPCInstr_Load(8, idst, zero_r1, mode64));
1820 add_to_sp( env, 16 );
1823 //set_FPU_rounding_default( env );
1829 HReg r_srcHi = newVRegF(env);
1830 HReg r_srcLo = newVRegF(env);
1831 HReg idst = newVRegI(env);
1832 HReg ftmp = newVRegF(env);
1833 PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
1835 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
1836 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2,
1838 addInstr(env, PPCInstr_DfpD128toD64(fpop, ftmp, r_srcHi, r_srcLo));
1841 sub_from_sp( env, 16 );
1842 addInstr(env, PPCInstr_FpLdSt(False/*store*/, 8, ftmp, zero_r1));
1843 addInstr(env, PPCInstr_Load(8, idst, zero_r1, True/*mode64*/));
1844 add_to_sp( env, 16 );
1859 HReg r_dst = newVRegI(env);
1860 HReg r_src = iselWordExpr_R(env, expr32, IEndianess);
1861 addInstr(env, PPCInstr_Alu(Palu_AND, r_dst,
1873 HReg r_dst = newVRegI(env);
1875 = iselWordExpr_AMode( env, mi.bindee[0], Ity_I16/*xfer*/,
1877 addInstr(env, PPCInstr_Load(2,r_dst,amode, mode64));
1888 HReg r_dst = newVRegI(env);
1889 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
1892 addInstr(env, PPCInstr_Alu(Palu_AND,r_dst,r_src,
1897 HReg r_dst = newVRegI(env);
1898 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
1900 addInstr(env,
1903 addInstr(env,
1911 HReg r_dst = newVRegI(env);
1912 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
1914 addInstr(env,
1917 addInstr(env,
1924 HReg r_dst = newVRegI(env);
1925 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
1928 addInstr(env,
1931 addInstr(env,
1937 HReg r_dst = newVRegI(env);
1938 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
1942 addInstr(env,
1952 HReg r_dst = newVRegI(env);
1953 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
1954 addInstr(env, PPCInstr_Unary(Pun_NOT,r_dst,r_src));
1960 iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg, IEndianess);
1963 HReg r_dst = newVRegI(env);
1964 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
1965 addInstr(env,
1974 iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg, IEndianess);
1978 return iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
1983 return iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
1989 HReg r_dst = newVRegI(env);
1990 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
1992 addInstr(env,
2000 iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg, IEndianess);
2007 iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg, IEndianess);
2015 HReg r_dst = newVRegI(env);
2016 PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg, IEndianess);
2017 addInstr(env, PPCInstr_Set(cond,r_dst));
2025 HReg r_dst = newVRegI(env);
2026 PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg, IEndianess);
2027 addInstr(env, PPCInstr_Set(cond,r_dst));
2028 addInstr(env,
2031 addInstr(env,
2039 HReg r_dst = newVRegI(env);
2040 PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg, IEndianess);
2041 addInstr(env, PPCInstr_Set(cond,r_dst));
2042 addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64bit shift*/,
2044 addInstr(env, PPCInstr_Shft(Pshft_SAR, False/*64bit shift*/,
2057 r_dst = newVRegI(env);
2058 r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
2059 addInstr(env, PPCInstr_Unary(op_clz,r_dst,r_src));
2070 r_dst = newVRegI(env);
2071 r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
2072 addInstr(env, PPCInstr_Unary(Pun_NEG,r_dst,r_src));
2073 addInstr(env, PPCInstr_Alu(Palu_OR, r_dst, r_dst, PPCRH_Reg(r_src)));
2078 HReg r_dst = newVRegI(env);
2079 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
2080 addInstr(env, PPCInstr_Unary(Pun_NEG,r_dst,r_src));
2081 addInstr(env, PPCInstr_Alu(Palu_OR, r_dst, r_dst, PPCRH_Reg(r_src)));
2082 addInstr(env, PPCInstr_Shft(Pshft_SAR, True/*32bit shift*/,
2088 HReg r_dst = newVRegI(env);
2089 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
2091 addInstr(env, PPCInstr_Unary(Pun_NEG,r_dst,r_src));
2092 addInstr(env, PPCInstr_Alu(Palu_OR, r_dst, r_dst, PPCRH_Reg(r_src)));
2093 addInstr(env, PPCInstr_Shft(Pshft_SAR, False/*64bit shift*/,
2100 HReg dst = newVRegI(env);
2101 HReg vec = iselVecExpr(env, e->Iex.Unop.arg, IEndianess);
2103 sub_from_sp( env, 32 ); // Move SP down 32 bytes
2106 r_aligned16 = get_sp_aligned16( env );
2122 addInstr(env,
2124 addInstr(env,
2127 add_to_sp( env, 32 ); // Reset SP
2135 HReg dst = newVRegI(env);
2136 HReg vec = iselVecExpr(env, e->Iex.Unop.arg, IEndianess);
2138 sub_from_sp( env, 32 ); // Move SP down 32 bytes
2141 r_aligned16 = get_sp_aligned16( env );
2146 addInstr(env,
2159 addInstr(env,
2165 add_to_sp( env, 32 ); // Reset SP
2174 return iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
2182 HReg fr_src = iselDblExpr(env, e->Iex.Unop.arg, IEndianess);
2183 HReg r_dst = newVRegI(env);
2185 sub_from_sp( env, 16 ); // Move SP down 16 bytes
2189 addInstr(env, PPCInstr_FpLdSt( False/*store*/, 8,
2192 addInstr(env, PPCInstr_Load( 8, r_dst, am_addr, mode64 ));
2194 add_to_sp( env, 16 ); // Reset SP
2206 HReg fr_src = iselFltExpr(env, e->Iex.Unop.arg, IEndianess);
2207 HReg r_dst = newVRegI(env);
2209 sub_from_sp( env, 16 ); // Move SP down 16 bytes
2213 addInstr(env, PPCInstr_FpLdSt( False/*store*/, 4,
2216 addInstr(env, PPCInstr_Load( 4, r_dst, am_addr, mode64 ));
2218 add_to_sp( env, 16 ); // Reset SP
2226 HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg, IEndianess);
2227 HReg r_dst = newVRegI(env);
2229 sub_from_sp( env, 16 ); // Move SP down 16 bytes
2233 addInstr(env, PPCInstr_FpLdSt( False/*store*/, 8,
2236 addInstr(env, PPCInstr_Load( 8, r_dst, am_addr, mode64 ));
2237 add_to_sp( env, 16 ); // Reset SP
2249 HReg r_dst = newVRegI(env);
2257 addInstr(env, mk_iMOVds_RR( argregs[argreg++],
2258 iselWordExpr_R(env, e->Iex.Unop.arg,
2263 addInstr(env, PPCInstr_Call( cc, (Addr)h_calc_BCDtoDPB,
2269 addInstr(env, PPCInstr_Call( cc, (Addr64)(fdescr[0]),
2274 addInstr(env, mk_iMOVds_RR(r_dst, argregs[0]));
2285 HReg r_dst = newVRegI(env);
2293 addInstr(env, mk_iMOVds_RR( argregs[argreg++],
2294 iselWordExpr_R(env, e->Iex.Unop.arg,
2300 addInstr(env, PPCInstr_Call( cc, (Addr)h_calc_DPBtoBCD,
2306 addInstr(env, PPCInstr_Call( cc, (Addr64)(fdescr[0]),
2311 addInstr(env, mk_iMOVds_RR(r_dst, argregs[0]));
2322 HReg fr_dst = newVRegI(env);
2323 HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg, IEndianess);
2324 HReg tmp = newVRegF(env);
2325 PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
2326 addInstr(env, PPCInstr_Dfp64Unary(Pfp_DXEX, tmp, fr_src));
2329 sub_from_sp( env, 16 );
2330 addInstr(env, PPCInstr_FpLdSt(False/*store*/, 8, tmp, zero_r1));
2331 addInstr(env, PPCInstr_Load(8, fr_dst, zero_r1, env->mode64));
2332 add_to_sp( env, 16 );
2336 HReg fr_dst = newVRegI(env);
2339 HReg tmp = newVRegF(env);
2340 PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
2342 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Unop.arg,
2344 addInstr(env, PPCInstr_ExtractExpD128(Pfp_DXEXQ, tmp,
2347 sub_from_sp( env, 16 );
2348 addInstr(env, PPCInstr_FpLdSt(False/*store*/, 8, tmp, zero_r1));
2349 addInstr(env, PPCInstr_Load(8, fr_dst, zero_r1, env->mode64));
2350 add_to_sp( env, 16 );
2364 HReg r_dst = newVRegI(env);
2367 addInstr(env, PPCInstr_Load( toUChar(sizeofIRType(ty)),
2376 = genGuestArrayOffset( env, e->Iex.GetI.descr,
2379 HReg r_dst = newVRegI(env);
2381 addInstr(env, PPCInstr_Load( toUChar(8),
2386 addInstr(env, PPCInstr_Load( toUChar(4),
2405 doHelperCall( &addToSp, &rloc, env, NULL/*guard*/,
2413 HReg r_dst = newVRegI(env);
2414 addInstr(env, mk_iMOVds_RR(r_dst, hregPPC_GPR3(mode64)));
2422 HReg r_dst = newVRegI(env);
2432 addInstr(env, PPCInstr_LI(r_dst, (ULong)l, mode64));
2440 typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1) {
2441 PPCRI* r1 = iselWordExpr_RI(env, e->Iex.ITE.iftrue, IEndianess);
2442 HReg r0 = iselWordExpr_R(env, e->Iex.ITE.iffalse, IEndianess);
2443 HReg r_dst = newVRegI(env);
2444 addInstr(env, mk_iMOVds_RR(r_dst,r0));
2445 PPCCondCode cc = iselCondCode(env, e->Iex.ITE.cond, IEndianess);
2446 addInstr(env, PPCInstr_CMov(cc, r_dst, r1));
2498 static Bool sane_AMode ( ISelEnv* env, PPCAMode* am )
2500 Bool mode64 = env->mode64;
2519 PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e, IRType xferTy,
2522 PPCAMode* am = iselWordExpr_AMode_wrk(env, e, xferTy, IEndianess);
2523 vassert(sane_AMode(env, am));
2528 static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e,
2531 IRType ty = typeOfIRExpr(env->type_env,e);
2533 if (env->mode64) {
2557 iselWordExpr_R(env, e->Iex.Binop.arg1,
2564 HReg r_base = iselWordExpr_R(env
2565 HReg r_idx = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
2581 iselWordExpr_R(env, e->Iex.Binop.arg1,
2588 HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
2589 HReg r_idx = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
2597 return PPCAMode_IR( 0, iselWordExpr_R(env,e,IEndianess) );
2610 static PPCRH* iselWordExpr_RH ( ISelEnv* env, Bool syned, IRExpr* e,
2613 PPCRH* ri = iselWordExpr_RH_wrk(env, syned, e, IEndianess);
2622 vassert(hregClass(ri->Prh.Reg.reg) == HRcGPR(env->mode64));
2631 static PPCRH* iselWordExpr_RH_wrk ( ISelEnv* env, Bool syned, IRExpr* e,
2636 IRType ty = typeOfIRExpr(env->type_env,e);
2638 ty == Ity_I32 || ((ty == Ity_I64) && env->mode64));
2646 case Ico_U64: vassert(env->mode64);
2665 return PPCRH_Reg( iselWordExpr_R ( env, e, IEndianess ) );
2675 static PPCRI* iselWordExpr_RI ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
2677 PPCRI* ri = iselWordExpr_RI_wrk(env, e, IEndianess);
2683 vassert(hregClass(ri->Pri.Reg) == HRcGPR(env->mode64));
2692 static PPCRI* iselWordExpr_RI_wrk ( ISelEnv* env, IRExpr* e,
2696 IRType ty = typeOfIRExpr(env->type_env,e);
2698 ty == Ity_I32 || ((ty == Ity_I64) && env->mode64));
2704 case Ico_U64: vassert(env->mode64);
2715 return PPCRI_Reg( iselWordExpr_R ( env, e, IEndianess ) );
2725 static PPCRH* iselWordExpr_RH5u ( ISelEnv* env, IRExpr* e,
2729 vassert(!env->mode64);
2730 ri = iselWordExpr_RH5u_wrk(env, e, IEndianess);
2738 vassert(hregClass(ri->Prh.Reg.reg) == HRcGPR(env->mode64));
2747 static PPCRH* iselWordExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e,
2750 IRType ty = typeOfIRExpr(env->type_env,e);
2762 return PPCRH_Reg( iselWordExpr_R ( env, e, IEndianess ) );
2772 static PPCRH* iselWordExpr_RH6u ( ISelEnv* env, IRExpr* e,
2776 vassert(env->mode64);
2777 ri = iselWordExpr_RH6u_wrk(env, e, IEndianess);
2785 vassert(hregClass(ri->Prh.Reg.reg) == HRcGPR(env->mode64));
2794 static PPCRH* iselWordExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e,
2797 IRType ty = typeOfIRExpr(env->type_env,e);
2809 return PPCRH_Reg( iselWordExpr_R ( env, e, IEndianess ) );
2819 static PPCCondCode iselCondCode ( ISelEnv* env, IRExpr* e,
2823 return iselCondCode_wrk(env,e, IEndianess);
2827 static PPCCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e,
2831 vassert(typeOfIRExpr(env->type_env,e) == Ity_I1);
2836 HReg r_zero = newVRegI(env);
2837 addInstr(env, PPCInstr_LI(r_zero, 0, env->mode64));
2838 addInstr(env, PPCInstr_Cmp(False/*unsigned*/, True/*32bit cmp*/,
2846 PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg, IEndianess);
2856 HReg src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
2857 HReg tmp = newVRegI(env);
2859 addInstr(env, PPCInstr_Alu(Palu_AND, tmp,
2861 addInstr(env, PPCInstr_Cmp(False/*unsigned*/, True/*32bit cmp*/,
2873 HReg arg = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
2874 HReg tmp = newVRegI(env);
2875 addInstr(env, PPCInstr_Alu(Palu_AND, tmp, arg,
2877 addInstr(env, PPCInstr_Cmp(False/*unsigned*/, True/*32bit cmp*/,
2887 HReg r1 = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
2888 addInstr(env, PPCInstr_Cmp(False/*unsigned*/, True/*32bit cmp*/,
2905 HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
2906 PPCRH* ri2 = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2, IEndianess);
2907 addInstr(env, PPCInstr_Cmp(syned, True/*32bit cmp*/,
2926 if (!env->mode64) {
2928 HReg tmp = newVRegI(env);
2929 iselInt64Expr( &hi, &lo, env, e->Iex.Unop.arg, IEndianess );
2930 addInstr(env, PPCInstr_Alu(Palu_OR, tmp, lo, PPCRH_Reg(hi)));
2931 addInstr(env, PPCInstr_Cmp(False/*sign*/, True/*32bit cmp*/,
2935 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
2936 addInstr(env, PPCInstr_Cmp(False/*sign*/, False/*64bit cmp*/,
2954 HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
2955 PPCRH* ri2 = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2, IEndianess);
2956 vassert(env->mode64);
2957 addInstr(env, PPCInstr_Cmp(syned, False/*64bit cmp*/,
2977 HReg arg = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
2978 HReg tmp = newVRegI(env);
2979 addInstr(env, PPCInstr_Alu(Palu_AND, tmp, arg,
2981 addInstr(env, PPCInstr_Cmp(False/*unsigned*/, True/*32bit cmp*/,
2988 HReg r_src = lookupIRTemp(env, e->Iex.RdTmp.tmp);
2989 HReg src_masked = newVRegI(env);
2990 addInstr(env,
2993 addInstr(env,
3016 ISelEnv* env
3018 vassert(env->mode64);
3019 iselInt128Expr_wrk(rHi, rLo, env, e, IEndianess);
3023 vassert(hregClass(*rHi) == HRcGPR(env->mode64));
3025 vassert(hregClass(*rLo) == HRcGPR(env->mode64));
3031 ISelEnv* env, IRExpr* e, IREndness IEndianess )
3034 vassert(typeOfIRExpr(env->type_env,e) == Ity_I128);
3038 lookupIRTempPair( rHi, rLo, env, e->Iex.RdTmp.tmp);
3048 HReg tLo = newVRegI(env);
3049 HReg tHi = newVRegI(env);
3051 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
3052 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
3053 addInstr(env, PPCInstr_MulL(False/*signedness irrelevant*/,
3056 addInstr(env, PPCInstr_MulL(syned,
3066 *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
3067 *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
3095 HReg* rLo, ISelEnv* env, IRExpr* e,
3098 vassert(!env->mode64);
3099 iselInt128Expr_to_32x4_wrk(rHi, rMedHi, rMedLo, rLo, env, e, IEndianess);
3115 ISelEnv* env, IRExpr* e,
3119 vassert(typeOfIRExpr(env->type_env,e) == Ity_I128);
3123 lookupIRTempQuad( rHi, rMedHi, rMedLo, rLo, env, e->Iex.RdTmp.tmp);
3132 iselInt64Expr(rHi, rMedHi, env, e->Iex.Binop.arg1, IEndianess);
3133 iselInt64Expr(rMedLo, rLo, env, e->Iex.Binop.arg2, IEndianess);
3153 ISelEnv* env, IRExpr* e,
3156 vassert(!env->mode64);
3157 iselInt64Expr_wrk(rHi, rLo, env, e, IEndianess);
3169 ISelEnv* env, IRExpr* e,
3173 vassert(typeOfIRExpr(env->type_env,e) == Ity_I64);
3177 HReg tLo = newVRegI(env);
3178 HReg tHi = newVRegI(env);
3179 HReg r_addr = iselWordExpr_R(env, e->Iex.Load.addr, IEndianess);
3180 vassert(!env->mode64);
3181 addInstr(env, PPCInstr_Load( 4/*byte-load*/,
3184 addInstr(env, PPCInstr_Load( 4/*byte-load*/,
3197 HReg tLo = newVRegI(env);
3198 HReg tHi = newVRegI(env);
3200 addInstr(env, PPCInstr_LI(tHi, (Long)(Int)wHi, False/*mode32*/));
3201 addInstr(env, PPCInstr_LI(tLo, (Long)(Int)wLo, False/*mode32*/));
3209 lookupIRTempPair( rHi, rLo, env, e->Iex.RdTmp.tmp);
3217 PPCAMode* am_addr4 = advance4(env, am_addr);
3218 HReg tLo = newVRegI(env);
3219 HReg tHi = newVRegI(env);
3220 addInstr(env, PPCInstr_Load( 4, tHi, am_addr, False/*mode32*/ ));
3221 addInstr(env, PPCInstr_Load( 4, tLo, am_addr4, False/*mode32*/ ));
3230 iselInt64Expr(&eXHi, &eXLo, env, e->Iex.ITE.iftrue, IEndianess);
3231 iselInt64Expr(&e0Hi, &e0Lo, env, e->Iex.ITE.iffalse, IEndianess);
3232 HReg tLo = newVRegI(env);
3233 HReg tHi = newVRegI(env);
3234 addInstr(env, mk_iMOVds_RR(tHi,e0Hi));
3235 addInstr(env, mk_iMOVds_RR(tLo,e0Lo));
3236 PPCCondCode cc = iselCondCode(env, e->Iex.ITE.cond, IEndianess);
3237 addInstr(env, PPCInstr_CMov(cc,tHi,PPCRI_Reg(eXHi)));
3238 addInstr(env, PPCInstr_CMov(cc,tLo,PPCRI_Reg(eXLo)));
3251 HReg tLo = newVRegI(env);
3252 HReg tHi = newVRegI(env);
3254 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1,
3256 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2,
3258 addInstr(env, PPCInstr_MulL(False/*signedness irrelevant*/,
3261 addInstr(env, PPCInstr_MulL(syned,
3274 HReg tLo = newVRegI(env);
3275 HReg tHi = newVRegI(env);
3278 iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1, IEndianess);
3279 iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2, IEndianess);
3280 addInstr(env, PPCInstr_Alu(op, tHi, xHi, PPCRH_Reg(yHi)));
3281 addInstr(env, PPCInstr_Alu(op, tLo, xLo, PPCRH_Reg(yLo)));
3290 HReg tLo = newVRegI(env);
3291 HReg tHi = newVRegI(env);
3292 iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1, IEndianess);
3293 iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2, IEndianess);
3294 addInstr(env, PPCInstr_AddSubC( True/*add*/, True /*set carry*/,
3296 addInstr(env, PPCInstr_AddSubC( True/*add*/, False/*read carry*/,
3305 *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
3306 *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
3311 HReg tLo = newVRegI(env);
3312 HReg tHi = newVRegI(env);
3313 HReg r1 = StackFramePtr(env->mode64);
3316 HReg fsrc = iselDblExpr(env, e->Iex.Binop.arg2,
3318 HReg ftmp = newVRegF(env);
3320 vassert(!env->mode64);
3322 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
3324 sub_from_sp( env, 16 );
3325 addInstr(env, PPCInstr_FpCftI(False/*F->I*/, False/*int64*/,
3328 addInstr(env, PPCInstr_FpLdSt(False/*store*/, 8, ftmp, zero_r1));
3329 addInstr(env, PPCInstr_Load(4, tHi, zero_r1, False/*mode32*/));
3330 addInstr(env, PPCInstr_Load(4, tLo, four_r1, False/*mode32*/));
3331 add_to_sp( env, 16 );
3334 //set_FPU_rounding_default( env );
3340 HReg tLo = newVRegI(env);
3341 HReg tHi = newVRegI(env);
3342 HReg r1 = StackFramePtr(env->mode64);
3345 HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess);
3346 HReg tmp = newVRegF(env);
3348 vassert(!env->mode64);
3349 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
3350 addInstr(env, PPCInstr_Dfp64Unary(Pfp_DCTFIX, tmp, fr_src));
3352 sub_from_sp( env, 16 );
3353 addInstr(env, PPCInstr_FpLdSt(False/*store*/, 8, tmp, zero_r1));
3354 addInstr(env, PPCInstr_Load(4, tHi, zero_r1, False/*mode32*/));
3355 addInstr(env, PPCInstr_Load(4, tLo, four_r1, False/*mode32*/));
3356 add_to_sp( env, 16 );
3363 HReg r_srcHi = newVRegF(env);
3364 HReg r_srcLo = newVRegF(env);
3365 HReg tLo = newVRegI(env);
3366 HReg tHi = newVRegI(env);
3367 HReg ftmp = newVRegF(env);
3368 PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
3369 PPCAMode* four_r1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) );
3371 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
3372 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2,
3374 addInstr(env, PPCInstr_DfpD128toD64(fpop, ftmp, r_srcHi, r_srcLo));
3377 sub_from_sp( env, 16 );
3378 addInstr(env, PPCInstr_FpLdSt(False/*store*/, 8, ftmp, zero_r1));
3379 addInstr(env, PPCInstr_Load(4, tHi, zero_r1, False/*mode32*/));
3380 addInstr(env, PPCInstr_Load(4, tLo, four_r1, False/*mode32*/));
3381 add_to_sp( env, 16 );
3399 HReg tmp1 = newVRegI(env);
3400 HReg tmp2 = newVRegI(env);
3401 iselInt64Expr(&argHi, &argLo, env, e->Iex.Unop.arg, IEndianess);
3403 addInstr(env, PPCInstr_Alu(Palu_OR, tmp1, argHi, PPCRH_Reg(argLo)));
3405 addInstr(env, PPCInstr_Unary(Pun_NEG,tmp2,tmp1));
3406 addInstr(env, PPCInstr_Alu(Palu_OR, tmp2, tmp2, PPCRH_Reg(tmp1)));
3407 addInstr(env, PPCInstr_Shft(Pshft_SAR, True/*32bit shift*/,
3417 HReg zero32 = newVRegI(env);
3418 HReg resHi = newVRegI(env);
3419 HReg resLo = newVRegI(env);
3420 iselInt64Expr(&argHi, &argLo, env, e->Iex.Unop.arg, IEndianess);
3421 vassert(env->mode64 == False);
3422 addInstr(env, PPCInstr_LI(zero32, 0, env->mode64));
3424 addInstr(env, PPCInstr_AddSubC( False/*sub*/, True/*set carry*/,
3426 addInstr(env, PPCInstr_AddSubC( False/*sub*/, False/*read carry*/,
3429 addInstr(env, PPCInstr_Alu(Palu_OR, resLo, resLo, PPCRH_Reg(argLo)));
3430 addInstr(env, PPCInstr_Alu(Palu_OR, resHi, resHi, PPCRH_Reg(argHi)));
3438 HReg tHi = newVRegI(env);
3439 HReg src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
3440 addInstr(env, PPCInstr_Shft(Pshft_SAR, True/*32bit shift*/,
3447 HReg tmp = newVRegF(env);
3448 HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg, IEndianess);
3449 HReg tLo = newVRegI(env);
3450 env);
3451 PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
3452 PPCAMode* four_r1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) );
3454 addInstr(env, PPCInstr_Dfp64Unary(Pfp_DXEX, tmp, fr_src));
3457 sub_from_sp( env, 16 );
3458 addInstr(env, PPCInstr_FpLdSt(False/*store*/, 8, tmp, zero_r1));
3459 addInstr(env, PPCInstr_Load(4, tHi, zero_r1, False/*mode32*/));
3460 addInstr(env, PPCInstr_Load(4, tLo, four_r1, False/*mode32*/));
3461 add_to_sp( env, 16 );
3469 HReg tmp = newVRegF(env);
3470 HReg tLo = newVRegI(env);
3471 HReg tHi = newVRegI(env);
3472 PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
3473 PPCAMode* four_r1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) );
3475 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Unop.arg, IEndianess);
3476 addInstr(env, PPCInstr_ExtractExpD128(Pfp_DXEXQ, tmp,
3480 sub_from_sp( env, 16 );
3481 addInstr(env, PPCInstr_FpLdSt(False/*store*/, 8, tmp, zero_r1));
3482 addInstr(env, PPCInstr_Load(4, tHi, zero_r1, False/*mode32*/));
3483 addInstr(env, PPCInstr_Load(4, tLo, four_r1, False/*mode32*/));
3484 add_to_sp( env, 16 );
3492 HReg tHi = newVRegI(env);
3493 HReg tLo = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
3494 addInstr(env, PPCInstr_LI(tHi, 0, False/*mode32*/));
3509 env, e->Iex.Unop.arg, IEndianess);
3524 env, e->Iex.Unop.arg, IEndianess);
3535 HReg tLo = newVRegI(env);
3536 HReg tHi = newVRegI(env);
3537 HReg vec = iselVecExpr(env, e->Iex.Unop.arg, IEndianess);
3539 sub_from_sp( env, 32 ); // Move SP down 32 bytes
3542 r_aligned16 = get_sp_aligned16( env );
3548 addInstr(env,
3552 addInstr(env,
3554 addInstr(env,
3557 add_to_sp( env, 32 ); // Reset SP
3565 HReg tLo = newVRegI(env);
3566 HReg tHi = newVRegI(env);
3567 PPCCondCode cond = iselCondCode(env, e->Iex.Unop.arg, IEndianess);
3568 addInstr(env, PPCInstr_Set(cond,tLo));
3569 addInstr(env, PPCInstr_Shft(Pshft_SHL, True/*32bit shift*/,
3571 addInstr(env, PPCInstr_Shft(Pshft_SAR, True/*32bit shift*/,
3573 addInstr(env, mk_iMOVds_RR(tHi, tLo));
3581 HReg tmpLo = newVRegI(env);
3582 HReg tmpHi = newVRegI(env);
3583 iselInt64Expr(&xHi, &xLo, env, e->Iex.Unop.arg, IEndianess);
3584 addInstr(env, PPCInstr_Unary(Pun_NOT,tmpLo,xLo));
3585 addInstr(env, PPCInstr_Unary(Pun_NOT,tmpHi,xHi));
3596 HReg fr_src = iselDblExpr(env, e->Iex.Unop.arg, IEndianess);
3597 HReg r_dstLo = newVRegI(env);
3598 HReg r_dstHi = newVRegI(env);
3600 sub_from_sp( env, 16 ); // Move SP down 16 bytes
3605 addInstr(env, PPCInstr_FpLdSt( False/*store*/, 8,
3609 addInstr(env, PPCInstr_Load( 4, r_dstHi,
3611 addInstr(env, PPCInstr_Load( 4, r_dstLo,
3616 add_to_sp( env, 16 ); // Reset SP
3621 HReg fr_src = iselDfp64Expr(env, e->Iex.Unop.arg, IEndianess);
3623 HReg r_dstLo = newVRegI(env);
3624 HReg r_dstHi = newVRegI(env);
3627 sub_from_sp( env, 16 ); // Move SP down 16 bytes
3632 addInstr(env, PPCInstr_FpLdSt( False/*store*/, 8,
3636 addInstr(env, PPCInstr_Load( 4, r_dstHi,
3638 addInstr(env, PPCInstr_Load( 4, r_dstLo,
3643 add_to_sp( env, 16 ); // Reset SP
3653 HReg tLo = newVRegI(env);
3654 HReg tHi = newVRegI(env);
3657 Bool mode64 = env->mode64;
3665 iselInt64Expr( &tmpHi, &tmpLo, env, e->Iex.Unop.arg, IEndianess );
3668 addInstr( env, mk_iMOVds_RR( argregs[argreg++], tmpHi ) );
3671 addInstr( env, mk_iMOVds_RR( argregs[argreg], tmpLo ) );
3676 addInstr( env, PPCInstr_Call( cc, (Addr)h_calc_BCDtoDPB,
3683 addInstr( env, PPCInstr_Call( cc, target,
3688 addInstr( env, mk_iMOVds_RR( tHi, argregs[argreg-1] ) );
3689 addInstr( env, mk_iMOVds_RR( tLo, argregs[argreg] ) );
3701 HReg tLo = newVRegI(env);
3702 HReg tHi = newVRegI(env);
3705 Bool mode64 = env->mode64;
3713 iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Unop.arg, IEndianess);
3716 addInstr(env, mk_iMOVds_RR( argregs[argreg++], tmpHi ));
3719 addInstr(env, mk_iMOVds_RR( argregs[argreg], tmpLo));
3724 addInstr(env, PPCInstr_Call( cc, (Addr)h_calc_DPBtoBCD,
3731 addInstr(env, PPCInstr_Call( cc, target, argiregs,
3735 addInstr(env, mk_iMOVds_RR(tHi, argregs[argreg-1]));
3736 addInstr(env, mk_iMOVds_RR(tLo, argregs[argreg]));
3761 static HReg iselFltExpr ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
3763 HReg r = iselFltExpr_wrk( env, e, IEndianess );
3773 static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
3775 Bool mode64 = env->mode64;
3777 IRType ty = typeOfIRExpr(env->type_env,e);
3781 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
3786 HReg r_dst = newVRegF(env);
3788 am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_F32/*xfer*/,
3790 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 4, r_dst, am_addr));
3795 HReg r_dst = newVRegF(env);
3797 GuestStatePtr(env->mode64) );
3798 addInstr(env, PPCInstr_FpLdSt( True/*load*/, 4, r_dst, am_addr ));
3831 HReg fsrc = iselDblExpr(env, e->Iex.Unop.arg, IEndianess);
3832 HReg fdst = newVRegF(env);
3833 PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
3835 sub_from_sp( env, 16 );
3837 addInstr(env, PPCInstr_FpLdSt( False/*store*/, 4,
3840 addInstr(env, PPCInstr_FpLdSt( True/*load*/, 4,
3842 add_to_sp( env, 16 );
3848 HReg fdst = newVRegF(env);
3849 HReg isrc = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
3850 HReg r1 = StackFramePtr(env->mode64);
3854 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
3856 sub_from_sp( env, 16 );
3858 addInstr(env, PPCInstr_Store(8, zero_r1, isrc, True/*mode64*/));
3859 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fdst, zero_r1));
3860 addInstr(env, PPCInstr_FpCftI(True/*I->F*/, False/*int64*/,
3864 add_to_sp( env, 16 );
3867 //set_FPU_rounding_default( env );
3871 HReg fdst = newVRegF(env);
3873 HReg r1 = StackFramePtr(env->mode64);
3877 iselInt64Expr(&isrcHi, &isrcLo, env, e->Iex.Binop.arg2, IEndianess);
3880 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
3882 sub_from_sp( env, 16 );
3884 addInstr(env, PPCInstr_Store(4, zero_r1, isrcHi, False/*mode32*/));
3885 addInstr(env, PPCInstr_Store(4, four_r1, isrcLo, False/*mode32*/));
3886 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fdst, zero_r1));
3887 addInstr(env, PPCInstr_FpCftI(True/*I->F*/, False/*int64*/,
3891 add_to_sp( env, 16 );
3894 //set_FPU_rounding_default( env );
3933 static HReg iselDblExpr ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
3935 HReg r = iselDblExpr_wrk( env, e, IEndianess );
3945 static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
3947 Bool mode64 = env->mode64;
3948 IRType ty = typeOfIRExpr(env->type_env,e);
3953 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
3974 HReg r_srcHi = newVRegI(env);
3975 HReg r_srcLo = newVRegI(env);
3976 addInstr(env, PPCInstr_LI(r_srcHi, u.u32x2[0], mode64));
3977 addInstr(env, PPCInstr_LI(r_srcLo, u.u32x2[1], mode64));
3978 return mk_LoadRR32toFPR( env, r_srcHi, r_srcLo );
3980 HReg r_src = newVRegI(env);
3981 addInstr(env, PPCInstr_LI(r_src, u.u64, mode64));
3982 return mk_LoadR64toFPR( env, r_src ); // 1*I64 -> F64
3988 HReg r_dst = newVRegF(env);
3991 am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_F64/*xfer*/,
3993 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, r_dst, am_addr));
3999 HReg r_dst = newVRegF(env);
4002 addInstr(env, PPCInstr_FpLdSt( True/*load*/, 8, r_dst, am_addr ));
4017 HReg r_dst = newVRegF(env);
4018 HReg r_srcML = iselDblExpr(env, e->Iex.Qop.details->arg2,
4020 HReg r_srcMR = iselDblExpr(env, e->Iex.Qop.details->arg3,
4022 HReg r_srcAcc = iselDblExpr(env, e->Iex.Qop.details->arg4,
4024 set_FPU_rounding_mode( env, e->Iex.Qop.details->arg1, IEndianess );
4025 addInstr(env, PPCInstr_FpMulAcc(fpop, r_dst,
4046 HReg r_dst = newVRegF(env);
4047 HReg r_srcL = iselDblExpr(env, triop->arg2, IEndianess);
4048 HReg r_srcR = iselDblExpr(env, triop->arg3, IEndianess);
4049 set_FPU_rounding_mode( env, triop->arg1, IEndianess );
4050 addInstr(env, PPCInstr_FpBinary(fpop, r_dst, r_srcL, r_srcR));
4062 HReg fr_dst = newVRegF(env);
4063 HReg fr_src = iselDblExpr(env, e->Iex.Binop.arg2, IEndianess);
4064 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4065 addInstr(env, PPCInstr_FpUnary(fpop, fr_dst, fr_src));
4073 HReg r_dst = newVRegF(env);
4074 HReg r_src = iselDblExpr(env, e->Iex.Binop.arg2, IEndianess);
4075 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4076 addInstr(env, PPCInstr_FpRSP(r_dst, r_src));
4077 //set_FPU_rounding_default( env );
4083 HReg fdst = newVRegF(env);
4084 HReg isrc = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
4085 HReg r1 = StackFramePtr(env->mode64);
4089 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4091 sub_from_sp( env, 16 );
4093 addInstr(env, PPCInstr_Store(8, zero_r1, isrc, True/*mode64*/));
4094 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fdst, zero_r1));
4095 addInstr(env, PPCInstr_FpCftI(True/*I->F*/, False/*int64*/,
4100 add_to_sp( env, 16 );
4103 //set_FPU_rounding_default( env );
4107 HReg fdst = newVRegF(env);
4109 HReg r1 = StackFramePtr(env->mode64);
4113 iselInt64Expr(&isrcHi, &isrcLo, env, e->Iex.Binop.arg2,
4117 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4119 sub_from_sp( env, 16 );
4121 addInstr(env, PPCInstr_Store(4, zero_r1, isrcHi, False/*mode32*/));
4122 addInstr(env, PPCInstr_Store(4, four_r1, isrcLo, False/*mode32*/));
4123 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fdst, zero_r1));
4124 addInstr(env, PPCInstr_FpCftI(True/*I->F*/, False/*int64*/,
4129 add_to_sp( env, 16 );
4132 //set_FPU_rounding_default( env );
4152 HReg fr_dst = newVRegF(env);
4153 HReg fr_src = iselDblExpr(env, e->Iex.Unop.arg, IEndianess);
4154 addInstr(env, PPCInstr_FpUnary(fpop, fr_dst, fr_src));
4166 iselInt64Expr( &r_srcHi, &r_srcLo, env, e->Iex.Unop.arg,
4168 return mk_LoadRR32toFPR( env, r_srcHi, r_srcLo );
4170 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
4171 return mk_LoadR64toFPR( env, r_src );
4180 HReg src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
4181 HReg fr_dst = newVRegF(env);
4184 sub_from_sp( env, 16 ); // Move SP down 16 bytes
4185 am_addr = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
4188 addInstr(env, PPCInstr_Store( 4, am_addr, src, env->mode64 ));
4192 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 4, fr_dst, am_addr));
4194 add_to_sp( env, 16 ); // Reset SP
4200 HReg res = iselFltExpr(env, e->Iex.Unop.arg, IEndianess);
4211 && typeOfIRExpr(env->type_env,e->Iex.ITE.cond) == Ity_I1) {
4212 HReg fr1 = iselDblExpr(env, e->Iex.ITE.iftrue, IEndianess);
4213 HReg fr0 = iselDblExpr(env, e->Iex.ITE.iffalse, IEndianess);
4214 HReg fr_dst = newVRegF(env);
4215 addInstr(env, PPCInstr_FpUnary( Pfp_MOV, fr_dst, fr0 ));
4216 PPCCondCode cc = iselCondCode(env, e->Iex.ITE.cond, IEndianess);
4217 addInstr(env, PPCInstr_FpCMov( cc, fr_dst, fr1 ));
4227 static HReg iselDfp32Expr(ISelEnv* env, IRExpr* e, IREndness IEndianess)
4229 HReg r = iselDfp32Expr_wrk( env, e, IEndianess );
4236 static HReg iselDfp32Expr_wrk(ISelEnv* env, IRExpr* e, IREndness IEndianess)
4238 Bool mode64 = env->mode64;
4239 IRType ty = typeOfIRExpr( env->type_env, e );
4246 HReg r_dst = newVRegF( env );
4249 addInstr( env, PPCInstr_FpLdSt( True/*load*/, 8, r_dst, am_addr ) );
4256 HReg r_dst = newVRegF(env);
4258 am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_D32/*xfer*/,
4260 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 4, r_dst, am_addr));
4267 HReg fr_dst = newVRegF(env);
4268 HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess);
4269 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4270 addInstr(env, PPCInstr_Dfp64Unary(Pfp_DRSP, fr_dst, fr_src));
4279 static HReg iselDfp64Expr(ISelEnv* env, IRExpr* e, IREndness IEndianess)
4281 HReg r = iselDfp64Expr_wrk( env, e, IEndianess );
4288 static HReg iselDfp64Expr_wrk(ISelEnv* env, IRExpr* e, IREndness IEndianess)
4290 Bool mode64 = env->mode64;
4291 IRType ty = typeOfIRExpr( env->type_env, e );
4298 return lookupIRTemp( env, e->Iex.RdTmp.tmp );
4303 HReg r_dst = newVRegF( env );
4306 addInstr( env, PPCInstr_FpLdSt( True/*load*/, 8, r_dst, am_addr ) );
4312 HReg r_dst = newVRegF(env);
4314 am_addr = iselWordExpr_AMode(env, e->Iex.Load.addr, Ity_D64/*xfer*/,
4316 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, r_dst, am_addr));
4322 HReg r_dst = newVRegF( env );
4327 HReg fr_dst = newVRegF(env);
4334 iselInt64Expr( &r_srcHi, &r_srcLo, env, e->Iex.Unop.arg,
4336 return mk_LoadRR32toFPR( env, r_srcHi, r_srcLo );
4338 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
4339 return mk_LoadR64toFPR( env, r_src );
4343 HReg fr_src = iselDfp32Expr(env, e->Iex.Unop.arg, IEndianess);
4344 addInstr(env, PPCInstr_Dfp64Unary(Pfp_DCTDP, fr_dst, fr_src));
4348 iselDfp128Expr( &r_dstHi, &r_dstLo, env, e->Iex.Unop.arg,
4352 iselDfp128Expr( &r_dstHi, &r_dstLo, env, e->Iex.Unop.arg,
4356 HReg fr_srcL = iselDblExpr(env, e->Iex.Binop.arg1, IEndianess);
4357 HReg fr_srcR = iselDblExpr(env, e->Iex.Binop.arg2, IEndianess);
4359 addInstr(env, PPCInstr_Dfp64Binary(Pfp_DIEX, fr_dst, fr_srcL,
4371 HReg fr_dst = newVRegF(env);
4381 HReg r_srcHi = newVRegF(env);
4382 HReg r_srcLo = newVRegF(env);
4384 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4385 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2,
4387 addInstr(env, PPCInstr_DfpD128toD64(fpop, fr_dst, r_srcHi, r_srcLo));
4391 HReg fr_src = newVRegF(env);
4392 PPCRI* r_rmc = iselWordExpr_RI(env, e->Iex.Binop.arg1, IEndianess);
4399 fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess);
4400 addInstr(env, PPCInstr_DfpRound(fr_dst, fr_src, r_rmc));
4404 HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess);
4405 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4406 addInstr(env, PPCInstr_Dfp64Unary(fpop, fr_dst, fr_src));
4410 HReg fr_src = newVRegF(env);
4411 PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
4413 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4414 sub_from_sp( env, 16 );
4418 HReg tmp = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
4420 addInstr(env, PPCInstr_Store(8, zero_r1, tmp, True/*mode64*/));
4423 PPCAMode* four_r1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) );
4425 iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Binop.arg2,
4427 addInstr(env, PPCInstr_Store(4, zero_r1, tmpHi, False/*mode32*/));
4428 addInstr(env, PPCInstr_Store(4, four_r1, tmpLo, False/*mode32*/));
4431 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fr_src, zero_r1));
4432 addInstr(env, PPCInstr_Dfp64Unary(fpop, fr_dst, fr_src));
4433 add_to_sp( env, 16 );
4444 HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg1, IEndianess);
4445 PPCRI* shift = iselWordExpr_RI(env, e->Iex.Binop.arg2, IEndianess);
4450 addInstr(env, PPCInstr_DfpShift(fpop, fr_dst, fr_src, shift));
4461 HReg fr_srcL = newVRegF(env);
4462 HReg fr_srcR = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess);
4463 PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
4464 sub_from_sp( env, 16 );
4466 if (env->mode64) {
4468 HReg tmp = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
4470 addInstr(env, PPCInstr_Store(8, zero_r1, tmp, True/*mode64*/));
4475 PPCAMode* four_r1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) );
4477 iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Binop.arg1,
4479 addInstr(env, PPCInstr_Store(4, zero_r1, tmpHi, False/*!mode64*/));
4480 addInstr(env, PPCInstr_Store(4, four_r1, tmpLo, False/*!mode64*/));
4482 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fr_srcL, zero_r1));
4483 addInstr(env, PPCInstr_Dfp64Binary(fpop, fr_dst, fr_srcL,
4485 add_to_sp( env, 16 );
4511 HReg r_dst = newVRegF( env );
4512 HReg r_srcL = iselDfp64Expr( env, triop->arg2, IEndianess );
4513 HReg r_srcR = iselDfp64Expr( env, triop->arg3, IEndianess );
4515 set_FPU_DFP_rounding_mode( env, triop->arg1, IEndianess );
4516 addInstr( env, PPCInstr_Dfp64Binary( fpop, r_dst, r_srcL, r_srcR ) );
4526 HReg r_dst = newVRegF(env);
4527 HReg r_srcL = iselDfp64Expr(env, triop->arg2, IEndianess);
4528 HReg r_srcR = iselDfp64Expr(env, triop->arg3, IEndianess);
4529 PPCRI* rmc = iselWordExpr_RI(env, triop->arg1, IEndianess);
4530 addInstr(env, PPCInstr_DfpQuantize(fpop, r_dst, r_srcL, r_srcR,
4535 HReg r_dst = newVRegF(env);
4536 HReg r_srcL = newVRegF(env);
4537 HReg r_srcR = iselDfp64Expr(env, triop->arg3, IEndianess);
4538 PPCRI* rmc = iselWordExpr_RI(env, triop->arg1, IEndianess);
4539 PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
4540 HReg i8_val = iselWordExpr_R(env, triop->arg2, IEndianess);
4543 sub_from_sp( env, 16 );
4545 addInstr(env, PPCInstr_Store(8, zero_r1, i8_val, True/*mode64*/));
4547 addInstr(env, PPCInstr_Store(4, zero_r1, i8_val, False/*mode32*/));
4549 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, r_srcL, zero_r1));
4550 add_to_sp( env, 16 );
4553 addInstr(env, PPCInstr_DfpQuantize(fpop, r_dst, r_srcL, r_srcR, rmc));
4562 static void iselDfp128Expr(HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e,
4565 iselDfp128Expr_wrk( rHi, rLo, env, e, IEndianess );
4571 static void iselDfp128Expr_wrk(HReg* rHi, HReg *rLo, ISelEnv* env, IRExpr* e,
4575 vassert( typeOfIRExpr(env->type_env,e) == Ity_D128 );
4579 lookupIRTempPair( rHi, rLo, env, e->Iex.RdTmp.tmp );
4584 HReg r_dstHi = newVRegF(env);
4585 HReg r_dstLo = newVRegF(env);
4588 HReg fr_src = newVRegF(env);
4589 PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
4592 if (env->mode64) {
4593 HReg tmp = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
4594 addInstr(env, PPCInstr_Store(8, zero_r1, tmp, True/*mode64*/));
4597 PPCAMode* four_r1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) );
4599 iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Unop.arg,
4601 addInstr(env, PPCInstr_Store(4, zero_r1, tmpHi, False/*mode32*/));
4602 addInstr(env, PPCInstr_Store(4, four_r1, tmpLo, False/*mode32*/));
4605 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fr_src, zero_r1));
4606 addInstr(env, PPCInstr_DfpI64StoD128(Pfp_DCFFIXQ, r_dstHi, r_dstLo,
4611 HReg r_src = iselDfp64Expr(env, e->Iex.Unop.arg, IEndianess);
4617 addInstr(env, PPCInstr_Dfp128Unary(Pfp_DCTQPQ, r_dstHi, r_dstLo,
4632 r_srcHi = iselDfp64Expr( env, e->Iex.Binop.arg1, IEndianess );
4633 r_srcLo = iselDfp64Expr( env, e->Iex.Binop.arg2, IEndianess );
4640 HReg fr_dst = newVRegF(env);
4642 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4643 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2,
4645 addInstr(env, PPCInstr_DfpD128toD64(fpop, fr_dst, r_srcHi, r_srcLo));
4656 HReg fr_dst_hi = newVRegF(env);
4657 HReg fr_dst_lo = newVRegF(env);
4658 PPCRI* shift = iselWordExpr_RI(env, e->Iex.Binop.arg2, IEndianess);
4661 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg1,
4667 addInstr(env, PPCInstr_DfpShift128(fpop, fr_dst_hi, fr_dst_lo,
4675 HReg r_dstHi = newVRegF(env);
4676 HReg r_dstLo = newVRegF(env);
4677 PPCRI* r_rmc = iselWordExpr_RI(env, e->Iex.Binop.arg1, IEndianess);
4680 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2,
4683 addInstr(env, PPCInstr_DfpRound128(r_dstHi, r_dstLo,
4690 HReg r_dstHi = newVRegF(env);
4691 HReg r_dstLo = newVRegF(env);
4692 HReg r_srcL = newVRegF(env);
4693 PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
4694 r_srcHi = newVRegF(env);
4695 r_srcLo = newVRegF(env);
4697 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2,
4701 if (env->mode64) {
4702 HReg tmp = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
4703 addInstr(env, PPCInstr_Store(8, zero_r1, tmp, True/*mode64*/));
4706 PPCAMode* four_r1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) );
4708 iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Unop.arg,
4710 addInstr(env, PPCInstr_Store(4, zero_r1, tmpHi, False/*mode32*/));
4711 addInstr(env, PPCInstr_Store(4, four_r1, tmpLo, False/*mode32*/));
4714 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, r_srcL, zero_r1));
4715 addInstr(env, PPCInstr_InsertExpD128(Pfp_DIEXQ,
4732 HReg r_dstHi = newVRegF(env);
4733 HReg r_dstLo = newVRegF(env);
4753 HReg r_srcRHi = newVRegV( env );
4754 HReg r_srcRLo = newVRegV( env );
4757 iselDfp128Expr( &r_dstHi, &r_dstLo, env, triop->arg2, IEndianess );
4758 iselDfp128Expr( &r_srcRHi, &r_srcRLo, env, triop->arg3, IEndianess );
4759 set_FPU_DFP_rounding_mode( env, triop->arg1, IEndianess );
4760 addInstr( env,
4773 HReg r_srcHi = newVRegF(env);
4774 HReg r_srcLo = newVRegF(env);
4775 PPCRI* rmc = iselWordExpr_RI(env, triop->arg1, IEndianess);
4778 iselDfp128Expr(&r_dstHi, &r_dstLo, env, triop->arg2, IEndianess);
4779 iselDfp128Expr(&r_srcHi, &r_srcLo, env, triop->arg3, IEndianess);
4782 addInstr(env, PPCInstr_DfpQuantize128(fpop, r_dstHi, r_dstLo,
4789 HReg r_srcHi = newVRegF(env);
4790 HReg r_srcLo = newVRegF(env);
4791 PPCRI* rmc = iselWordExpr_RI(env, triop->arg1, IEndianess);
4792 PPCAMode* zero_r1 = PPCAMode_IR( 0, StackFramePtr(env->mode64) );
4793 PPCAMode* four_r1 = PPCAMode_IR( 4, StackFramePtr(env->mode64) );
4794 HReg i8_val = iselWordExpr_R(env, triop->arg2, IEndianess);
4795 HReg r_zero = newVRegI( env );
4797 iselDfp128Expr(&r_srcHi, &r_srcLo, env, triop->arg3, IEndianess);
4805 sub_from_sp( env, 16 );
4807 if (env->mode64)
4808 addInstr(env, PPCInstr_Store(4, four_r1, i8_val, True/*mode64*/));
4810 addInstr(env, PPCInstr_Store(4, four_r1, i8_val, False/*mode32*/));
4815 addInstr( env, PPCInstr_LI( r_zero, 0, env->mode64 ) );
4816 addInstr(env
4817 addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, r_dstLo, zero_r1));
4819 add_to_sp( env, 16 );
4822 addInstr(env, PPCInstr_DfpQuantize128(fpop, r_dstHi, r_dstLo,
4839 static HReg iselVecExpr ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
4841 HReg r = iselVecExpr_wrk( env, e, IEndianess );
4851 static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e, IREndness IEndianess )
4853 Bool mode64 = env->mode64;
4856 IRType ty = typeOfIRExpr(env->type_env,e);
4861 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
4867 HReg dst = newVRegV(env);
4868 addInstr(env,
4889 HReg Vhi = newVRegV(env);
4890 HReg Vlo = newVRegV(env);
4891 HReg Vp = newVRegV(env);
4892 HReg v_dst = newVRegV(env);
4894 HReg rB_plus_15 = newVRegI(env);
4897 rB = iselWordExpr_R( env, e->Iex.Load.addr, IEndianess );
4900 addInstr(env, PPCInstr_AvLdSt( True/*load*/, 16, Vhi,
4905 addInstr(env, PPCInstr_AvSh( False/*right shift*/, Vp,
4909 addInstr(env, PPCInstr_AvSh( True/*left shift*/, Vp,
4913 addInstr(env, PPCInstr_Alu( Palu_ADD, rB_plus_15,
4917 addInstr(env, PPCInstr_AvLdSt( True/*load*/, 16, Vlo,
4922 addInstr(env, PPCInstr_AvPerm( v_dst, Vlo, Vhi, Vp ));
4925 addInstr(env, PPCInstr_AvPerm( v_dst, Vhi, Vlo, Vp ));
4934 HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess);
4935 HReg dst = newVRegV(env);
4936 addInstr(env, PPCInstr_AvUnary(Pav_NOT, dst, arg));
4941 HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess);
4942 HReg zero = newVRegV(env);
4943 HReg dst = newVRegV(env);
4944 addInstr(env, PPCInstr_AvBinary(Pav_XOR, zero, zero, zero));
4945 addInstr(env, PPCInstr_AvBin8x16(Pav_CMPEQU, dst, arg, zero));
4946 addInstr(env, PPCInstr_AvUnary(Pav_NOT, dst, dst));
4951 HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess);
4952 HReg zero = newVRegV(env);
4953 HReg dst = newVRegV(env);
4954 addInstr(env, PPCInstr_AvBinary(Pav_XOR, zero, zero, zero));
4955 addInstr(env, PPCInstr_AvBin16x8(Pav_CMPEQU, dst, arg, zero));
4956 addInstr(env, PPCInstr_AvUnary(Pav_NOT, dst, dst));
4961 HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess);
4962 HReg zero = newVRegV(env);
4963 HReg dst = newVRegV(env);
4964 addInstr(env, PPCInstr_AvBinary(Pav_XOR, zero, zero, zero));
4965 addInstr(env, PPCInstr_AvBin32x4(Pav_CMPEQU, dst, arg, zero));
4966 addInstr(env, PPCInstr_AvUnary(Pav_NOT, dst, dst));
4971 HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess);
4972 HReg zero = newVRegV(env);
4973 HReg dst = newVRegV(env);
4974 addInstr(env, PPCInstr_AvBinary(Pav_XOR, zero, zero, zero));
4975 addInstr(env, PPCInstr_AvBin64x2(Pav_CMPEQU, dst, arg, zero));
4976 addInstr(env, PPCInstr_AvUnary(Pav_NOT, dst, dst));
4992 HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess);
4993 HReg dst = newVRegV(env);
4994 addInstr(env, PPCInstr_AvUn32Fx4(fpop, dst, arg));
5000 HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
5001 HReg dst = newVRegV(env);
5003 sub_from_sp( env, 32 ); // Move SP down
5006 r_aligned16 = get_sp_aligned16( env );
5013 r_zeros = newVRegI(env);
5014 addInstr(env, PPCInstr_LI(r_zeros, 0x0, mode64));
5016 addInstr(env, PPCInstr_Store( 4, am_off0, r_src, mode64 ));
5018 addInstr(env, PPCInstr_Store( 4, am_off0, r_zeros, mode64 ));
5019 addInstr(env, PPCInstr_Store( 4, am_off4, r_zeros, mode64 ));
5020 addInstr(env, PPCInstr_Store( 4, am_off8, r_zeros, mode64 ));
5024 addInstr(env, PPCInstr_Store( 4, am_off12, r_zeros, mode64 ));
5026 addInstr(env, PPCInstr_Store( 4, am_off12, r_src, mode64 ));
5030 addInstr(env, PPCInstr_AvLdSt( True/*ld*/, 4, dst, am_off0 ));
5032 addInstr(env, PPCInstr_AvLdSt( True/*ld*/, 4, dst, am_off12 ));
5034 add_to_sp( env, 32 ); // Reset SP
5041 return mk_AvDuplicateRI(env, e->Iex.Unop.arg, IEndianess);
5045 HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess);
5046 HReg dst = newVRegV(env);
5047 addInstr(env, PPCInstr_AvCipherV128Unary(op, dst, arg));
5058 HReg arg = iselVecExpr(env, e->Iex.Unop.arg, IEndianess);
5059 HReg dst = newVRegV(env);
5060 addInstr(env, PPCInstr_AvUnary(op, dst, arg));
5076 HReg dst = newVRegV(env);
5078 sub_from_sp( env, 32 ); // Move SP down
5081 r_aligned16 = get_sp_aligned16( env );
5088 iselInt64Expr(&r1, &r0, env, e->Iex.Binop.arg2, IEndianess);
5089 addInstr(env, PPCInstr_Store( 4, am_off12, r0, mode64 ));
5090 addInstr(env, PPCInstr_Store( 4, am_off8, r1, mode64 ));
5092 iselInt64Expr(&r3, &r2, env, e->Iex.Binop.arg1, IEndianess);
5093 addInstr(env, PPCInstr_Store( 4, am_off4, r2, mode64 ));
5094 addInstr(env, PPCInstr_Store( 4, am_off0, r3, mode64 ));
5097 addInstr(env, PPCInstr_AvLdSt(True/*ld*/, 16, dst, am_off0));
5099 add_to_sp( env, 32 ); // Reset SP
5102 HReg rHi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
5103 HReg rLo = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
5104 HReg dst = newVRegV(env);
5108 sub_from_sp( env, 32 ); // Move SP down
5111 r_aligned16 = get_sp_aligned16( env );
5117 addInstr(env, PPCInstr_Store( 8, am_off0, rLo, mode64 ));
5118 addInstr(env, PPCInstr_Store( 8, am_off8, rHi, mode64 ));
5120 addInstr(env, PPCInstr_Store( 8, am_off0, rHi, mode64 ));
5121 addInstr(env, PPCInstr_Store( 8, am_off8, rLo, mode64 ));
5124 addInstr(env, PPCInstr_AvLdSt(True/*ld*/, 16, dst, am_off0));
5126 add_to_sp( env, 32 ); // Reset SP
5138 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5139 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5140 HReg dst = newVRegV(env);
5141 addInstr(env, PPCInstr_AvBin32Fx4(fpop, dst, argL, argR));
5146 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5147 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5148 HReg dst = newVRegV(env);
5154 HReg isNanLR = newVRegV(env);
5155 HReg isNanL = isNan(env, argL, IEndianess);
5156 HReg isNanR = isNan(env, argR, IEndianess);
5157 addInstr(env, PPCInstr_AvBinary(Pav_OR, isNanLR,
5160 addInstr(env, PPCInstr_AvBin32Fx4(Pavfp_CMPGTF, dst,
5162 addInstr(env, PPCInstr_AvBinary(Pav_OR, dst, dst, isNanLR));
5163 addInstr(env, PPCInstr_AvUnary(Pav_NOT, dst, dst));
5171 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5172 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5173 HReg dst = newVRegV(env);
5174 addInstr(env, PPCInstr_AvBinary(op, dst, arg1, arg2));
5203 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5204 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5205 HReg dst = newVRegV(env);
5206 addInstr(env, PPCInstr_AvBin8x16(op, dst, arg1, arg2));
5238 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5239 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5240 HReg dst = newVRegV(env);
5241 addInstr(env, PPCInstr_AvBin16x8(op, dst, arg1, arg2));
5276 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5277 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5278 HReg dst = newVRegV(env);
5279 addInstr(env, PPCInstr_AvBin32x4(op, dst, arg1, arg2));
5303 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5304 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5305 HReg dst = newVRegV(env);
5306 addInstr(env, PPCInstr_AvBin64x2(op, dst, arg1, arg2));
5313 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5314 HReg dst = newVRegV(env);
5315 HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2, IEndianess);
5316 addInstr(env, PPCInstr_AvBin8x16(op, dst, r_src, v_shft));
5324 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5325 HReg dst = newVRegV(env);
5326 HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2, IEndianess);
5327 addInstr(env, PPCInstr_AvBin16x8(op, dst, r_src, v_shft));
5335 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5336 HReg dst = newVRegV(env);
5337 HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2, IEndianess);
5338 addInstr(env, PPCInstr_AvBin32x4(op, dst, r_src, v_shft));
5346 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5347 HReg dst = newVRegV(env);
5348 HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2, IEndianess);
5349 addInstr(env, PPCInstr_AvBin64x2(op, dst, r_src, v_shft));
5356 HReg dst = newVRegV(env);
5357 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5358 HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2, IEndianess);
5360 addInstr(env, PPCInstr_AvBinary(op, dst, r_src, v_shft));
5365 HReg dst = newVRegV(env);
5366 HReg v_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5367 HReg v_ctl = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5368 addInstr(env, PPCInstr_AvPerm(dst, v_src, v_src, v_ctl));
5377 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5378 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5379 HReg dst = newVRegV(env);
5380 addInstr(env, PPCInstr_AvCipherV128Binary(op, dst, arg1, arg2));
5387 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5388 HReg dst = newVRegV(env);
5389 PPCRI* s_field = iselWordExpr_RI(env, e->Iex.Binop.arg2, IEndianess);
5390 addInstr(env, PPCInstr_AvHashV128Binary(op, dst, arg1, s_field));
5404 HReg arg1 = iselVecExpr(env, triop->arg1, IEndianess);
5405 HReg arg2 = iselVecExpr(env, triop->arg2, IEndianess);
5406 HReg dst = newVRegV(env);
5407 PPCRI* ps = iselWordExpr_RI(env, triop->arg3, IEndianess);
5408 addInstr(env, PPCInstr_AvBCDV128Trinary(op, dst, arg1, arg2, ps));
5417 HReg argL = iselVecExpr(env, triop->arg2, IEndianess);
5418 HReg argR = iselVecExpr(env, triop->arg3, IEndianess);
5419 HReg dst = newVRegV(env);
5426 set_FPU_rounding_mode(env, triop->arg1, IEndianess);
5427 addInstr(env, PPCInstr_AvBin32Fx4(fpop, dst, argL, argR));
5440 return generate_zeroes_V128(env);
5443 return generate_ones_V128(env);
5449 env->hwcaps));
5459 static void iselStmt ( ISelEnv* env, IRStmt* stmt, IREndness IEndianess )
5461 Bool mode64 = env->mode64;
5472 IRType tya = typeOfIRExpr(env->type_env, stmt->Ist.Store.addr);
5473 IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data);
5486 = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/,
5488 HReg r_src = iselWordExpr_R(env, stmt->Ist.Store.data, IEndianess);
5489 addInstr(env, PPCInstr_Store( toUChar(sizeofIRType(tyd)),
5495 = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/,
5497 HReg fr_src = iselDblExpr(env, stmt->Ist.Store.data, IEndianess);
5498 addInstr(env,
5504 = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/,
5506 HReg fr_src = iselFltExpr(env, stmt->Ist.Store.data, IEndianess);
5507 addInstr(env,
5513 = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/,
5515 HReg fr_src = iselDfp64Expr(env, stmt->Ist.Store.data, IEndianess);
5516 addInstr(env,
5522 = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/,
5524 HReg fr_src = iselDfp32Expr(env, stmt->Ist.Store.data, IEndianess);
5525 addInstr(env,
5531 = iselWordExpr_AMode(env, stmt->Ist.Store.addr, tyd/*of xfer*/,
5533 HReg v_src = iselVecExpr(env, stmt->Ist.Store.data, IEndianess);
5534 addInstr(env,
5543 HReg r_addr = iselWordExpr_R(env, stmt->Ist.Store.addr, IEndianess);
5544 iselInt64Expr( &rHi32, &rLo32, env, stmt->Ist.Store.data,
5546 addInstr(env, PPCInstr_Store( 4/*byte-store*/,
5550 addInstr(env, PPCInstr_Store( 4/*byte-store*/,
5561 IRType ty = typeOfIRExpr(env->type_env, stmt->Ist.Put.data);
5564 HReg r_src = iselWordExpr_R(env, stmt->Ist.Put.data, IEndianess);
5567 addInstr(env, PPCInstr_Store( toUChar(sizeofIRType(ty)),
5575 PPCAMode* am_addr4 = advance4(env, am_addr);
5576 iselInt64Expr(&rHi,&rLo, env, stmt->Ist.Put.data, IEndianess);
5577 addInstr(env, PPCInstr_Store( 4, am_addr, rHi, mode64 ));
5578 addInstr(env, PPCInstr_Store( 4, am_addr4, rLo, mode64 ));
5584 HReg v_src = iselVecExpr(env, stmt->Ist.Put.data, IEndianess);
5587 addInstr(env,
5592 HReg fr_src = iselDblExpr(env, stmt->Ist.Put.data, IEndianess);
5595 addInstr(env, PPCInstr_FpLdSt( False/*store*/, 8,
5601 HReg fr_src = iselDfp32Expr( env, stmt->Ist.Put.data, IEndianess );
5604 addInstr( env, PPCInstr_FpLdSt( False/*store*/, 8,
5609 HReg fr_src = iselDfp64Expr( env, stmt->Ist.Put.data, IEndianess );
5612 addInstr( env, PPCInstr_FpLdSt( False/*store*/, 8, fr_src, am_addr ) );
5624 env, puti->descr,
5627 IRType ty = typeOfIRExpr(env->type_env, puti->data);
5629 HReg r_src = iselWordExpr_R(env, puti->data, IEndianess);
5630 addInstr(env, PPCInstr_Store( toUChar(8),
5635 HReg r_src = iselWordExpr_R(env, puti->data, IEndianess);
5636 addInstr(env, PPCInstr_Store( toUChar(4),
5646 IRType ty = typeOfIRTemp(env->type_env, tmp);
5649 HReg r_dst = lookupIRTemp(env, tmp);
5650 HReg r_src = iselWordExpr_R(env, stmt->Ist.WrTmp.data, IEndianess);
5651 addInstr(env, mk_iMOVds_RR( r_dst, r_src ));
5657 iselInt64Expr(&r_srcHi,&r_srcLo, env, stmt->Ist.WrTmp.data,
5659 lookupIRTempPair( &r_dstHi, &r_dstLo, env, tmp);
5660 addInstr(env, mk_iMOVds_RR(r_dstHi, r_srcHi) );
5661 addInstr(env, mk_iMOVds_RR(r_dstLo, r_srcLo) );
5666 iselInt128Expr(&r_srcHi,&r_srcLo, env, stmt->Ist.WrTmp.data,
5668 lookupIRTempPair( &r_dstHi, &r_dstLo, env, tmp);
5669 addInstr(env, mk_iMOVds_RR(r_dstHi, r_srcHi) );
5670 addInstr(env, mk_iMOVds_RR(r_dstLo, r_srcLo) );
5679 env, stmt->Ist.WrTmp.data, IEndianess);
5682 &r_dstLo, env, tmp);
5684 addInstr(env, mk_iMOVds_RR(r_dstHi, r_srcHi) );
5685 addInstr(env, mk_iMOVds_RR(r_dstMedHi, r_srcMedHi) );
5686 addInstr(env, mk_iMOVds_RR(r_dstMedLo, r_srcMedLo) );
5687 addInstr(env, mk_iMOVds_RR(r_dstLo, r_srcLo) );
5691 PPCCondCode cond = iselCondCode(env, stmt->Ist.WrTmp.data,
5693 HReg r_dst = lookupIRTemp(env, tmp);
5694 addInstr(env, PPCInstr_Set(cond, r_dst));
5698 HReg fr_dst = lookupIRTemp(env, tmp);
5699 HReg fr_src = iselDblExpr(env, stmt->Ist.WrTmp.data, IEndianess);
5700 addInstr(env, PPCInstr_FpUnary(Pfp_MOV, fr_dst, fr_src));
5704 HReg fr_dst = lookupIRTemp(env, tmp);
5705 HReg fr_src = iselFltExpr(env, stmt->Ist.WrTmp.data, IEndianess);
5706 addInstr(env, PPCInstr_FpUnary(Pfp_MOV, fr_dst, fr_src));
5710 HReg fr_dst = lookupIRTemp(env, tmp);
5711 HReg fr_src = iselDfp32Expr(env, stmt->Ist.WrTmp.data, IEndianess);
5712 addInstr(env, PPCInstr_Dfp64Unary(Pfp_MOV, fr_dst, fr_src));
5716 HReg v_dst = lookupIRTemp(env, tmp);
5717 HReg v_src = iselVecExpr(env, stmt->Ist.WrTmp.data, IEndianess);
5718 addInstr(env, PPCInstr_AvUnary(Pav_MOV, v_dst, v_src));
5722 HReg fr_dst = lookupIRTemp( env, tmp );
5723 HReg fr_src = iselDfp64Expr( env, stmt->Ist.WrTmp.data, IEndianess );
5724 addInstr( env, PPCInstr_Dfp64Unary( Pfp_MOV, fr_dst, fr_src ) );
5729 // lookupDfp128IRTempPair( &fr_dstHi, &fr_dstLo, env, tmp );
5730 lookupIRTempPair( &fr_dstHi, &fr_dstLo, env, tmp );
5731 iselDfp128Expr( &fr_srcHi, &fr_srcLo, env, stmt->Ist.WrTmp.data,
5733 addInstr( env, PPCInstr_Dfp64Unary( Pfp_MOV, fr_dstHi, fr_srcHi ) );
5734 addInstr( env, PPCInstr_Dfp64Unary( Pfp_MOV, fr_dstLo, fr_srcLo ) );
5743 IRType tyRes = typeOfIRTemp(env->type_env, res);
5744 IRType tyAddr = typeOfIRExpr(env->type_env, stmt->Ist.LLSC.addr);
5755 HReg r_addr = iselWordExpr_R( env, stmt->Ist.LLSC.addr, IEndianess );
5756 HReg r_dst = lookupIRTemp(env, res);
5758 addInstr(env, PPCInstr_LoadL( 1, r_dst, r_addr, mode64 ));
5762 addInstr(env, PPCInstr_LoadL( 2, r_dst, r_addr, mode64 ));
5766 addInstr(env, PPCInstr_LoadL( 4, r_dst, r_addr, mode64 ));
5770 addInstr(env, PPCInstr_LoadL( 8, r_dst, r_addr, mode64 ));
5776 HReg r_res = lookupIRTemp(env, res); /* :: Ity_I1 */
5777 HReg r_a = iselWordExpr_R(env, stmt->Ist.LLSC.addr, IEndianess);
5778 HReg r_src = iselWordExpr_R(env, stmt->Ist.LLSC.storedata,
5780 HReg r_tmp = newVRegI(env);
5781 IRType tyData = typeOfIRExpr(env->type_env,
5797 addInstr(env, PPCInstr_StoreC( size,
5799 addInstr(env, PPCInstr_MfCR( r_tmp ));
5800 addInstr(env, PPCInstr_Shft(
5802 env->mode64 ? False : True
5810 addInstr(env, PPCInstr_Alu(
5829 retty = typeOfIRTemp(env->type_env, d->tmp);
5852 doHelperCall( &addToSp, &rloc, env, d->guard, d->cee, retty, d->args,
5868 HReg r_dst = lookupIRTemp(env, d->tmp);
5869 addInstr(env, mk_iMOVds_RR(r_dst, hregPPC_GPR3(mode64)));
5878 HReg r_dst = lookupIRTemp(env, d->tmp);
5879 addInstr(env, mk_iMOVds_RR(r_dst, hregPPC_GPR3(mode64)));
5887 lookupIRTempPair( &r_dstHi, &r_dstLo, env, d->tmp);
5888 addInstr(env, mk_iMOVds_RR(r_dstHi, hregPPC_GPR3(mode64)));
5889 addInstr(env, mk_iMOVds_RR(r_dstLo, hregPPC_GPR4(mode64)));
5901 HReg dst = lookupIRTemp(env, d->tmp);
5903 addInstr(env, PPCInstr_AvLdSt( True/*load*/, 16, dst, am ));
5904 add_to_sp(env, addToSp);
5917 addInstr(env, PPCInstr_MFence());
5948 PPCCondCode cc = iselCondCode(env, stmt->Ist.Exit.guard, IEndianess);
5956 if (env->chainingAllowed) {
5962 ? (((Addr64)stmt->Ist.Exit.dst->Ico.U64) > (Addr64)env->max_ga)
5963 : (((Addr32)stmt->Ist.Exit.dst->Ico.U32) > (Addr32)env->max_ga);
5965 addInstr(env, PPCInstr_XDirect(
5973 HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst),
5975 addInstr(env, PPCInstr_XAssisted(r, amCIA, cc, Ijk_Boring));
5993 HReg r = iselWordExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst),
5995 addInstr(env, PPCInstr_XAssisted(r, amCIA, cc,
6019 static void iselNext ( ISelEnv* env,
6036 vassert(cdst->tag == (env->mode64 ? Ico_U64 :Ico_U32));
6039 PPCAMode* amCIA = PPCAMode_IR(offsIP, hregPPC_GPR31(env->mode64));
6040 if (env->chainingAllowed) {
6045 = env->mode64
6046 ? (((Addr64)cdst->Ico.U64) > (Addr64)env->max_ga)
6047 : (((Addr32)cdst->Ico.U32) > (Addr32)env->max_ga);
6049 addInstr(env, PPCInstr_XDirect(
6050 env->mode64 ? (Addr64)cdst->Ico.U64
6057 HReg r = iselWordExpr_R(env, next, IEndianess);
6058 addInstr(env, PPCInstr_XAssisted(r, amCIA, always,
6068 HReg r = iselWordExpr_R(env, next, IEndianess);
6069 PPCAMode* amCIA = PPCAMode_IR(offsIP, hregPPC_GPR31(env->mode64));
6070 if (env->chainingAllowed) {
6071 addInstr(env, PPCInstr_XIndir(r, amCIA, always));
6073 addInstr(env, PPCInstr_XAssisted(r, amCIA, always,
6095 HReg r = iselWordExpr_R(env, next, IEndianess);
6096 PPCAMode* amCIA = PPCAMode_IR(offsIP, hregPPC_GPR31(env->mode64));
6097 addInstr(env, PPCInstr_XAssisted(r, amCIA, always, jk));
6131 ISelEnv* env;
6167 env = LibVEX_Alloc_inline(sizeof(ISelEnv));
6168 env->vreg_ctr = 0;
6171 env->mode64 = mode64;
6174 env->code = newHInstrArray();
6176 /* Copy BB's type env. */
6177 env->type_env = bb->tyenv;
6185 env->n_vregmap = bb->tyenv->types_used;
6186 env->vregmapLo = LibVEX_Alloc_inline(env->n_vregmap * sizeof(HReg));
6187 env->vregmapMedLo = LibVEX_Alloc_inline(env->n_vregmap * sizeof(HReg));
6189 env->vregmapMedHi = NULL;
6190 env->vregmapHi = NULL;
6192 env->vregmapMedHi = LibVEX_Alloc_inline(env->n_vregmap * sizeof(HReg));
6193 env->vregmapHi = LibVEX_Alloc_inline(env->n_vregmap * sizeof(HReg));
6197 env->chainingAllowed = chainingAllowed;
6198 env->max_ga = max_ga;
6199 env->hwcaps = hwcaps_host;
6200 env->previous_rm = NULL;
6201 env->vbi = vbi;
6206 for (i = 0; i < env->n_vregmap; i++) {
6257 env->vregmapLo[i] = hregLo;
6258 env->vregmapMedLo[i] = hregMedLo;
6260 env->vregmapMedHi[i] = hregMedHi;
6261 env->vregmapHi[i] = hregHi;
6264 env->vreg_ctr = j;
6269 addInstr(env, PPCInstr_EvCheck(amCounter, amFailAddr));
6276 addInstr(env, PPCInstr_ProfInc());
6281 iselStmt(env, bb->stmts[i], IEndianess);
6283 iselNext(env, bb->next, bb->jumpkind, bb->offsIP, IEndianess);
6286 env->code->n_vregs = env->vreg_ctr;
6287 return env->code;
